HC210 datasheet(37/228 Pages) ALTERA

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Altera Corporation

3–1

September 2008

Preliminary

3. Boundary-Scan Support

IEEE Std. 1149.1

(JTAG)

Boundary-Scan

Support

All HardCopy® II structured ASICs provide Joint Test Action Group

(JTAG) boundary-scan test (BST) circuitry that complies with the IEEE

Std. 1149.1-1990 specification. The BST architecture offers the capability

to efficiently test components on printed circuit boards (PCBs) with tight

lead spacing by testing pin connections, without using physical test

probes, and capturing functional data while a device is in normal

operation. Boundary-scan cells in a device can force signals onto pins, or

capture data from pin or core logic signals. Forced test data is serially

shifted into the boundary-scan cells. Captured data is serially shifted out

and externally compared to expected results.

A device using the JTAG interface uses four required pins,

TDI, TDO, TMS,

and

TCK, and one optional pin, TRST. The TCK pin has an internal weak

pull-down resistor, while the

TDI, TMS, and TRST pins have weak

internal pull-up resistors. The

TDO output is powered by VCCIO.

HardCopy II devices support the JTAG instructions shown in Table 3–1.

Table 3–1. HardCopy II JTAG Instructions (Part 1 of 2)

JTAG Instruction

Instruction Code

Description

SAMPLE/PRELOAD

00 0000 0101

Allows a snapshot of signals at the

device pins to be captured and

examined during normal device

operation, and permits an initial data

pattern to be output at the device

pins.

EXTEST (1)

00 0000 1111

Allows the external circuitry and

board-level interconnects to be

tested by forcing a test pattern at the

output pins and capturing test results

at the input pins.

BYPASS

11 1111 1111

Places the 1-bit

BYPASS register

between the

TDI and TDO pins,

which allows the BST data to pass

synchronously through selected

devices to adjacent devices during

normal device operation.

H51017-2.4

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