HC210 datasheet(61/228 Pages) ALTERA

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Altera Corporation

4–19

September 2008

On-Chip Termination Specifications

On-Chip

Termination

Specifications

Table 4–29 defines the specification for internal termination specification

when using series or differential on-chip termination for HC210W

devices only.

Table 4–29. Series On-Chip Termination Specification for I/O Banks Supporting Memory Interface IOEs for

HC210W

Notes (1), (2), (3)

Symbol

Description

Conditions

Resistance Tolerance

Commercial

Max

Industrial

Max

Unit

Ω RS

3.3/2.5

Internal series termination with

calibration (25-

Ω setting)

VCC IO = 3.3/2.5 V

± 10

± 15

Internal series termination

without calibration (25-

Ω setting)

VCC IO = 3.3/2.5 V

± 30

Ω R

3.3/2.5

Internal series termination with

calibration (50-

Ω setting)

VCC IO = 3.3/2.5 V

± 10

± 15

Internal series termination

without calibration (50-

Ω setting)

VCC IO = 3.3/2.5 V

± 30

Ω R

1.8

Internal series termination with

calibration (25-

Ω setting)

VCC IO = 1.8 V

± 10

± 15

Internal series termination

without calibration (25-

Ω setting)

VCC IO = 1.8 V

± 30

Ω R

1.8

Internal series termination with

calibration (50-

Ω setting)

VCC IO = 1.8 V

± 10

± 15

Internal series termination

without calibration (50-

Ω setting)

VCC IO = 1.8 V

± 30

Ω R

1.5

Internal series termination with

calibration (50-

Ω setting)

VCC IO = 1.5 V

± 13

± 15

Internal series termination

without calibration (50-

Ω setting)

VCC IO = 1.5 V

± 36

Notes to Table 4–29:

(1)

For information on which I/O banks support memory interface IOEs, refer to the Description, Architecture, and

Features chapter in the HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook.

(2)

The resistance tolerances for calibrated SOCT and POCT are at the time of initial of calibration. If the temperature

or voltage changes over time, the tolerance may also change.

(3)

This table applies only to the HC210W device.

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