HC210 datasheet(77/228 Pages) ALTERA

77 / 228 page

Altera Corporation

4–35

September 2008

HighSpeed I/O Specifications

HighSpeed I/O

Specifications

Table 4–39 provides high-speed timing specifications definitions.

Differential

SSTL-2 Class I

(3)

OCT 50

280

—

280

MHz

Differential

SSTL-2 Class II

(3)

OCT 25

280

—

280

MHz

Differential

SSTL-18 Class I

(3)

OCT 50

230

—

230

MHz

Differential

SSTL-18 Class II

(3)

OCT 25

220

—

220

MHz

1.8-V Differential

HSTL Class I (3)

OCT 50

270

—

270

MHz

1.8-V Differential

HSTL Class II (3)

OCT 25

210

—

210

MHz

1.5-V Differential

HSTL Class I (3)

OCT 50

190

—

190

MHz

Notes to Table 4–38:

(1)

The toggle rate applies to 0 pF output load for all I/O standards except for LVDS and HyperTransport technology

on row I/O pins. For LVDS and HyperTransport technology on row I/O pins, the toggle rates apply to load from

0 to 5 pF.

(2)

CLK [1, 3, 9, 11] and FPLL_CLK are dedicated input clocks, and excluded from this table.

(3)

Like Stratix II devices, differential HSTL and SSTL is supported only on the column

CLK, PLL_OUT and memory

interface

DQS IOE pins. For HC210 and HC220, only the top column clock pins support differential HSTL and SSTL.

(4)

These numbers are preliminary and pending further silicon characterization.

Table 4–38. HardCopy II Maximum Output Clock Rate for HC210W using OCT

Notes (1), (4) (Part 2 of 2)

I/O Standard

Drive

Strength

Memory

Interface

IOEs

High

Speed

IOEs

General Purpose

IOEs

CLK [0,

2, 8,

10] (2)

CLK

[4..7,

12..15]

PLL_OUT

Unit

Bottom

Column

Right

Row

Table 4–39. HighSpeed Timing Specifications and Definitions (Part 1 of 2)

HighSpeed Timing Specifications

Definitions

Highspeed receiver/transmitter input and output clock period.

fHSCLK

Highspeed receiver/transmitter input and output clock frequency.

De-serialization factor (width of parallel data bus).

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