HC210 datasheet(34/228 Pages) ALTERA

34 / 228 page

2–26

Altera Corporation

Preliminary

September 2008

HardCopy Series Handbook, Volume 1

The SERDES and DPA circuitry and functionality is the same in

HardCopy II devices as in Stratix II FPGAs. HardCopy II devices support

differential I/O standards at rates up to 1 Gbps when using DPA, and at

rates up to 840 Mbps when not using DPA. Table 2–13 provides the

number of differential channels per HardCopy II device.

HardCopy II high-speed IOEs, which are on the left and/or right sides of

the device, support fewer programmable drive strengths than Stratix II

side IOEs. The programmable drive strengths available vary depending

on the I/O standard being used. The options are listed in Table 2–14.

High-speed IOEs support non-calibrated on-chip series termination and

differential termination on the receiver channels. 50- and 25-

Ω on-chip

series termination is available for 3.3- or 2.5-V I/O standards. 50-

on-chip series termination is available for 1.8- and 1.5-V I/O standards

(pending characterization).

Table 2–13. Number of Differential Channels in HardCopy II Devices

Notes (1), (2)

Channel

HC210W

HC210

HC220

HC230

HC240

484-Pin

FineLine

BGA (Wire-

Bond)

484-Pin

FineLine

BGA

672-Pin

FineLine

BGA

780-Pin

FineLine

BGA

1,020-Pin

FineLine

BGA

1,020-Pin

FineLine

BGA

1,508-Pin

FineLine

BGA

Transmitter

channels

116

Receiver

channels

116

Notes to Table 2–13:

(1)

The pin count does not include dedicated PLL input and output pins.

(2)

The total number of receiver channels includes the non-dedicated clock channels that can optionally be used as

data channels.

Table 2–14. Programmable Drive Strength Support for High-Speed IOEs

I/O Standard

Programmable Drive Strength Options (mA)

3.3-V LVTTL

4, 8, 12

3.3-V LVCMOS

4, 8

2.5-V LVTTL/LVCMOS

4, 8, 12

1.8-V LVTTL/LVCMOS

2, 4, 6, 8

1.5-V LVCMOS

2, 4

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