HC210 datasheet(3/228 Pages) ALTERA

3 / 228 page

Altera Corporation

1–1

September 2008

Preliminary

1. Introduction to HardCopy II

Devices

Introduction

HardCopy® II devices are low-cost, high-performance structured ASICs

with pin-outs, densities, and architecture that complement Stratix® II

devices. HardCopy II device features, such as phase-locked loops (PLLs),

memory, and I/O elements (IOEs), are functionally and electrically

equivalent to the Stratix II FPGA features. The combination of Stratix II

FPGAs for in-system prototype and design verification, HardCopy II

devices for high-volume production, and the Quartus® II software for

design, provide a complete, low-risk design solution.

HardCopy II devices improve on the successful and proven methodology

of the two previous generations of HardCopy series devices. Altera®

HardCopy II devices use the same base arrays across multiple designs for

a given device density and are customized using only two metal layers.

HardCopy II devices offer up to 90% cost reduction compared to Stratix II

FPGA prototypes.

The Quartus II software provides a complete set of tools, common for

both designing Stratix II FPGA prototypes and for quickly migrating the

design to a HardCopy II companion device. HardCopy II devices are also

supported through other front-end design tools from Synopsys,

Synplicity, and Mentor Graphics®.

Feature

Overview

HardCopy II structured ASICs are manufactured on a 1.2 V, 90 nm

all-layer-copper metal fabrication process (up to nine layers of metal).

HardCopy II devices offer the following features:

■

Fine-grained HCell architecture resulting in a low-cost,

high-performance, low-power structured ASIC

■

Customized using only two metal layers for fast turn-around times

and low non-recurring expenses (NRE)

■

Fully tested prototypes are available in approximately 10 to 12 weeks

from the date of your design submission

■

Support for instant-on or instant-on-after-50-ms power-up modes

■

Preserves the design functionality of a Stratix II FPGA prototype

■

1,000,000 to 3,600,000 usable gates for both logic and DSP functions

H51015-2.6

HC210 Datasheet(PDF) 3 Page - Altera Corporation

HC210 Datasheet(HTML) 3 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL