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HC210 Datasheet(PDF) 134 Page - Altera Corporation |
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HC210 Datasheet(HTML) 134 Page - Altera Corporation |
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134 / 228 page ![]() 6–6 Altera Corporation September 2008 HardCopy Series Handbook, Volume 1 This example shows what is, perhaps, the simplest way to execute the HardCopy II design flow. If you have developed and applied the design I/O, location and timing constraints for the project, these constraints are included during script execution. f For more information on the Quartus II executables and command-line options, refer to the Command-Line Executables chapter in the Quartus II Scripting Reference Manual and the Command-Line Scripting section in volume 2 of the Quartus II Handbook. The HardCopy II Design Flow The Quartus II software supports both HardCopy II first and Stratix II first design flows. The Stratix II first flow involves the following: ■ Compiling for the Stratix II FPGA prototype ■ Verifying the Stratix II FPGA prototype ■ Migrating the prototype design to a HardCopy II design ■ Compiling the HardCopy II design ■ Transferring your HardCopy II files to the Altera® Design Center The Hardcopy II first flow is similar, but starts with compiling the HardCopy II target device. Once the HardCopy II compile completes successfully, the design is migrated to the Stratix II target. The HardCopy II design flow in the Quartus II software is shown in Figure 6–1. To begin a design, create a new project and revision for the Stratix II FPGA prototype. Apply Quartus II settings together with I/O assignments and timing constraints. Compile the Stratix II prototype revision (synthesis, place and route, and assembly) to produce a complete layout, with timing closure and free from errors. You can now perform any additional functional and timing verification necessary and then implement and verify the prototype in hardware. Once the FPGA prototype is verified, you can compile the HardCopy II design. Begin by creating a HardCopy II companion revision for the FPGA prototype: 1. Create a HardCopy II companion revision for the FPGA prototype. All design settings and constraints are automatically migrated to the new companion revision. 2. Compile the HardCopy II revision. As the compile runs, the Design Assistant checks for errors. When the compile completes, you should correct errors and resolve failures that appear in the Quartus II reports. |
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