HC210 datasheet(171/228 Pages) ALTERA

171 / 228 page

Altera Corporation

7–7

September 2008

HardCopy II Timing Closure Methodology

Figure 7–1. Stratix II First Timing Closure Flow Note (1)

Note to Figure 7–1:

(1)

Timing constraints are required in Stratix II revision and HardCopy II revision. The TimeQuest timing analyzer

supports industry-standard SDC files (.sdc) and Classic Timing Analyzer supports Quartus Setting File (.qsf).

As you can see from Figure 7–1, timing constraints are used very early in

the Quartus II design flow. During the Stratix II FPGA prototype

compilation, these constraints are used as the timing target for

timing-driven compilation. When the compilation is complete, the

TimeQuest timing analyzer or Classic Timing Analyzer reports timing

results for your design. Any failed timing reports mean that you must

either modify your timing constraints, change your compile settings and

recompile, or both. In addition, the timing constraint checkers in both

TimeQuest and Classic Timing Analyzer report the unconstrained timing

paths. See “Using the TimeQuest Timing Analyzer” on page 7–8 for

details. For timing verification in third-party tools, the Quartus II

Stratix II Revision

Timing Constraints

Compilation

Constraint Coverage Checks

Static Timing Analysis

FPGA Prototyping

HardCopy II Revision

Timing Constraints

Industry Standard

SDC Timing

Constraints

Stratix II Design Setup

Compilation

Constraint Coverage Checks

Static Timing Analysis

HardCopy Design Center

Handoff

Revision Comparison

HardCopy II Design Setup

HC210 Datasheet(PDF) 171 Page - Altera Corporation