 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AS3524 Datasheet(PDF) 114 Page - ams AG |
|
|
|||||||||||||||||||||||||||||
AS3524 Datasheet(HTML) 114 Page - ams AG |
|
|
114 / 124 page  AS3524 C21 / C22 austriamicrosystems Data Sheet, Confidential © 2003-2006, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.11 114 - 124 Ball Nr. BGA180 Ball Name PAD Type I/O Ball Description ide_iordy I IDE IO ready signal used by device to extend host data transfer cycles naf_wp_n O NAND FLASH write protect not M12 ide_intrq D IO ST PD LSR I IDE interrupt request used by device to interrupt the host controller naf_ce0_n O NAND FLASH chip enable M11 ide_cs0_n D IO ST LSR O IDE chip select 0 used by the host to select command block registers in the device naf_ce1_n O NAND FLASH chip enable P11 ide_cs1_n D IO ST LSR O IDE chip select 1 used by the host to select control block registers in the device naf_ce2_n O NAND FLASH chip enable T11 ide_hiown D IO ST LSR O IDE host IO write strobe naf_ce3_n O NAND FLASH chip enable V11 ide_hiorn D IO ST LSR O IDE host IO read strobe naf_we_n O NAND FLASH write enable not P12 ide_dackn D IO ST LSR O IDE DMA acknowledge used by the host to initiate DMA data transfers naf_re_n O NAND FLASH read enable not T12 ide_npcblid D IO ST LSR I IDE primary channel cable ID detect naf_bsy_n I NAND FLASH ready / busy not V12 ide_nscblid D IO ST LSR I IDE secondary channel cable ID select E18 ide_ha[0] D OUT LSR O IDE host address F18 ide_ha[1] D OUT LSR O IDE host address G18 ide_ha[2] D OUT LSR O IDE host address G16 ide_reset_n D OUT LSR O IDE reset not, used by the host to reset the device I2S Output N5 i2so_sdata D OUT LSR O IS2 data output, data output from digital core to audio sub system L3 i2so_sclk D OUT LSR O I2S serial clock, clock output from digital core to audio sub system T7 i2so_lrck D OUT LSR O I2S left/right clock, clock output from digital core to audio sub system M3 i2so_mclk D OUT LSR O I2S master clock, clock output from digital core to audio sub system I2S Input M5 i2si_sdata D IN ST I I2S data input, data output from audio sub system to digital core i2si_sclk_out O I2S master serial clock serial clock output for external ADC if AS3525 is I2S master K3 i2si_sclk_in D IO ST LSR I I2S slave serial clock serial clock input for external ADC if AS3525 is I2S slave i2si_lrck_out O I2S master, left/right clock left/right clock output for external ADC if AS3525 is I2S master P7 i2si_lrck_in D IO ST LSR I I2S slave, left/right clock left/right clock input for external ADC if AS3525 is I2S master L5 i2si_mclk D OUT LSR O I2S master, master clock J3 i2si_sdata_in D IN ST PD I I2S data input data input from external audio ADC |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
