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AS3524 Datasheet(PDF) 111 Page - ams AG |
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AS3524 Datasheet(HTML) 111 Page - ams AG |
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111 / 124 page ![]() AS3524 C21 / C22 austriamicrosystems Data Sheet, Confidential © 2003-2006, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.11 111 - 124 Ball Nr. BGA180 Ball Name PAD Type I/O Ball Description For testing purpose only, has to be set to “0”. P3 id_dig D IN ST (PU) I USB mini receptacle identifier Has to be connected to USB jack ID pin. Port A H5 xpa[0] D IO ST PD LSR IO GPIO IO, Port A J5 xpa[1] D IO ST PD LSR IO GPIO IO, Port A K5 xpa[2] D IO ST PD LSR IO GPIO IO, Port A K7 xpa[3] D IO ST PD LSR IO GPIO IO, Port A L7 xpa[4] D IO ST PD LSR IO GPIO IO, Port A M7 xpa[5] D IO ST PD LSR IO GPIO IO, Port A M8 xpa[6] D IO ST PD LSR IO GPIO IO, Port A P8 xpa[7] D IO ST PD LSR IO GPIO IO, Port A Port B / DISPLAY / UART xpb[0] IO GPIO IO, Port B mpmc_stcs1mw[0 ]* I static memory chip memory width setting for boot loader 0: 8 bit data bus 1: 16 bit data bus The value is latched at reset. T13 dbop_c0 D IO ST PD LSR O DISPLAY control output xpb[1] IO GPIO IO, Port B mpmc_stcs1pol* I static memory chip select polarity setting for boot loader 0: active LOW chip select 1: active high chip select The value is latched at reset. T14 dbop_c1 D IO ST PD LSR O DISPLAY control output xpb[2] IO GPIO IO, Port B mpmc_stcs1pb* I static memory byte lane polarity setting for boot loader 0: HIGH for reads, LOW for writes, used for we_n access 1: LOW for reads, LOW for writes, used for upper and lower byte access The value is latched at reset. T15 dbop_c2 D IO ST PD LSR O DISPLAY control output xpb[3] IO GPIO IO, Port B mpmc_rel1config* I test mode configuration (for testing purpose only !!!) The value is latched at reset. V13 dbop_c3 D IO ST PD LSR O DISPLAY control output xpb[4] IO GPIO IO, Port B V14 dbop_d[8] D IO ST PD LSR IO DISPLAY data input/output (high byte) xpb[5] IO GPIO IO, Port B V15 dbop_d[9] D IO ST PD LSR IO DISPLAY data input/output (high byte) xpb[6] IO GPIO IO, Port B uart_rxd I UART receive line V17 dbop_d[10] D IO ST PU LSR IO DISPLAY data input/output (high byte) xpb[7] IO GPIO IO, Port B uart_txd O UART transmit line V18 dbop_d[11] D IO ST PU LSR IO DISPLAY data input/output (high byte) Port C / DISPLAY / 2-WIRE SERIAL G5 xpc[0] D IO ST PD LSR IO GPIO IO, Port C |
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