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AS3524 Datasheet(PDF) 115 Page - ams AG |
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AS3524 Datasheet(HTML) 115 Page - ams AG |
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115 / 124 page  AS3524 C21 / C22 austriamicrosystems Data Sheet, Confidential © 2003-2006, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.11 115 - 124 Ball Nr. BGA180 Ball Name PAD Type I/O Ball Description spdif_data_in I SPDIF data input data input for SPDIF to I2S conversion Audio Subsystem IRQ T6 INTRQ D IN ST I interrupt input JTAG Debugging IF T8 jtag_trst_n D IN ST PD I JTAG reset not T9 jtag_tms D IN ST PU I JTAG mode select V9 jtag_tck D IN ST PU I JTAG clock V10 jtag_tdi D IN ST PU I JTAG data input T10 jtag_tdo D IO ST PU LSR O JTAG data output External Memory IF A1 mpmc_addr[0] D OUT LSR LV O EXT. MEMORY address line C3 mpmc_addr[1] D OUT LSR LV O EXT. MEMORY address line A2 mpmc_addr[2] D OUT LSR LV O EXT. MEMORY address line E5 mpmc_addr[3] D OUT LSR LV O EXT. MEMORY address line A3 mpmc_addr[4] D OUT LSR LV O EXT. MEMORY address line E6 mpmc_addr[5] D OUT LSR LV O EXT. MEMORY address line A4 mpmc_addr[6] D OUT LSR LV O EXT. MEMORY address line J7 mpmc_addr[7] D OUT LSR LV O EXT. MEMORY address line C4 mpmc_addr[8] D OUT LSR LV O EXT. MEMORY address line H7 mpmc_addr[9] D OUT LSR LV O EXT. MEMORY address line A5 mpmc_addr[10] D OUT LSR LV O EXT. MEMORY address line G7 mpmc_addr[11] D OUT LSR LV O EXT. MEMORY address line C5 mpmc_addr[12] D OUT LSR LV O EXT. MEMORY address line E7 mpmc_addr[13] D OUT LSR LV O EXT. MEMORY address line A6 mpmc_addr[14] D OUT LSR LV O EXT. MEMORY address line G8 mpmc_addr[15] D OUT LSR LV O EXT. MEMORY address line C6 mpmc_addr[16] D OUT LSR LV O EXT. MEMORY address line E8 mpmc_addr[17] D OUT LSR LV O EXT. MEMORY address line A7 mpmc_addr[18] D OUT LSR LV O EXT. MEMORY address line G9 mpmc_addr[19] D OUT LSR LV O EXT. MEMORY address line C7 mpmc_addr[20] D OUT LSR LV O EXT. MEMORY address line M9 mpmc_cke[0] D OUT LSR LV O EXT. MEMORY clock enable0 used for SDRAM devices only M10 mpmc_cke[1] D OUT LSR LV O EXT. MEMORY clock enable 1 used for SDRAM devices only A9 mpmc_clk[0] D OUT LSR LV O EXT. MEMORY clock 0 used for SDRAM devices only A10 mpmc_clk[1] D OUT LSR LV O EXT. MEMORY clock 1 used for SDRAM devices only C9 mpmc_fbclkin D IO ST PD LSR LV O EXT. MEMORY feedback clock used for SDRAM devices only E9 mpmc_dqm[0] D OUT LSR LV O EXT. MEMORY data mask 0 used for SDRAM devices and static memories E10 mpmc_dqm[1] D OUT LSR LV O EXT. MEMORY data mask 1 used for SDRAM devices and static memories C10 mpmc_cas_n D OUT LSR LV O EXT. MEMORY column address strobe not used for SDRAM devices only J9 mpmc_dycs_n[0] D OUT LSR LV O EXT. MEMORY dynamic memory chip select 0 not used for SDRAM devices only |
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