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AS3524 Datasheet(PDF) 113 Page - ams AG |
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AS3524 Datasheet(HTML) 113 Page - ams AG |
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113 / 124 page  AS3524 C21 / C22 austriamicrosystems Data Sheet, Confidential © 2003-2006, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.11 113 - 124 Ball Nr. BGA180 Ball Name PAD Type I/O Ball Description P6 i2c_audio_sck D IO ST PU LSR O 2-wire serial audio master clock line used for controlling the audio/PMU sub system P5 i2c_audio_sda D IO ST PU LSR O 2-wire serial audio master data line used for controlling the audio/PMU sub system Serial Synchronous Port ssp_fssout O SSP master, frame or slave select E14 ssp_fssin D IO ST PU LSR I SSP slave, frame select ssp_clkout O SSP master, clock line F14 ssp_clkin D IO ST PU LSR I SSP slave, clock line E16 ssp_rxd D IO ST PU LSR I SSP receive data input F16 ssp_txd D IO ST PU LSR O SSP transmit data output NandFlash / IDE naf_d[0] IO NAND FLASH data line (low byte) K18 ide_hd[0] D IO ST PD LSR IO IDE data line (low byte) naf_d[1] IO NAND FLASH data line (low byte) K16 ide_hd[1] D IO ST PD LSR IO IDE data line (low byte) naf_d[2] IO NAND FLASH data line (low byte) J14 ide_hd[2] D IO ST PD LSR IO IDE data line (low byte) naf_d[3] IO NAND FLASH data line (low byte) J12 ide_hd[3] D IO ST PD LSR IO IDE data line (low byte) naf_d[4] IO NAND FLASH data line (low byte) J18 ide_hd[4] D IO ST PD LSR IO IDE data line (low byte) naf_d[5] IO NAND FLASH data line (low byte) J16 ide_hd[5] D IO ST PD LSR IO IDE data line (low byte) naf_d[6] IO NAND FLASH data line (low byte) H14 ide_hd[6] D IO ST PD LSR IO IDE data line (low byte) naf_d[7] IO NAND FLASH data line (low byte) G14 ide_hd[7] D IO ST PD LSR IO IDE data line (low byte) naf_d[8] IO NAND FLASH data line (high byte) K12 ide_hd[8] D IO ST PD LSR IO IDE data line (high byte) naf_d[9] IO NAND FLASH data line (high byte) K14 ide_hd[9] D IO ST PD LSR IO IDE data line (high byte) naf_d[10] IO NAND FLASH data line (high byte) L16 ide_hd[10] D IO ST PD LSR IO IDE data line (high byte) naf_d[11] IO NAND FLASH data line (high byte) L18 ide_hd[11] D IO ST PD LSR IO IDE data line (high byte) naf_d[12] IO NAND FLASH data line (high byte) L12 ide_hd[12] D IO ST PD LSR IO IDE data line (high byte) naf_d[13] IO NAND FLASH data line (high byte) L14 ide_hd[13] D IO ST PD LSR IO IDE data line (high byte) naf_d[14] IO NAND FLASH data line (high byte) M16 ide_hd[14] D IO ST PD LSR IO IDE data line (high byte) naf_d[15] IO NAND FLASH data line (high byte) M18 ide_hd[15] D IO ST PD LSR IO IDE data line (high byte) naf_cle O NAND FLASH command latch enable M14 ide_dmarq D IO ST LSR I IDE DMA request used for DMA data transfers between host and device N14 naf_ale D IO ST LSR O NAND FLASH address latch enable |
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