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82G33 Datasheet(PDF) 252 Page - Intel Corporation

Part # 82G33
Description  Graphics and Memory Controller Hub
PDF  437 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82G33 Datasheet(HTML) 252 Page - Intel Corporation

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Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
252
Datasheet
8.1.15
CAPPOINT—Capabilities Pointer
B/D/F/Type:
0/2/0/PCI
Address Offset:
34h
Default Value:
90h
Access:
RO
Size:
8 bits
Bit
Access &
Default
Description
7:0
RO
90h
Capabilities Pointer Value (CPV): This field contains an offset into
the function's PCI Configuration Space for the first item in the New
Capabilities Linked List, the MSI Capabilities ID registers at address
90h or the Power Management capability at D0h.
This value is determined by the configuration in CAPL[0].
8.1.16
INTRLINE—Interrupt Line
B/D/F/Type:
0/2/0/PCI
Address Offset:
3Ch
Default Value:
00h
Access:
RW
Size:
8 bits
Bit
Access &
Default
Description
7:0
RW
00h
Interrupt Connection (INTCON): This field is used to
communicate interrupt line routing information. POST software
writes the routing information into this register as it initializes and
configures the system. The value in this register indicates to which
input of the system interrupt controller the device's interrupt pin is
connected.
8.1.17
INTRPIN—Interrupt Pin
B/D/F/Type:
0/2/0/PCI
Address Offset:
3Dh
Default Value:
01h
Access:
RO
Size:
8 bits
Bit
Access &
Default
Description
7:0
RO
01h
Interrupt Pin (INTPIN): As a single function device, the IGD
specifies INTA# as its interrupt pin.
01h = INTA#.



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