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82G33 Datasheet(PDF) 248 Page - Intel Corporation |
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82G33 Datasheet(HTML) 248 Page - Intel Corporation |
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248 / 437 page  Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 248 Datasheet 8.1.7 CLS—Cache Line Size B/D/F/Type: 0/2/0/PCI Address Offset: 0Ch Default Value: 00h Access: RO Size: 8 bits The IGD does not support this register as a PCI slave. Bit Access & Default Description 7:0 RO 00h Cache Line Size (CLS): This field is hardwired to 0s. The IGD as a PCI compliant master does not use the Memory Write and Invalidate command and, in general, does not perform operations based on cache line size. 8.1.8 MLT2—Master Latency Timer B/D/F/Type: 0/2/0/PCI Address Offset: 0Dh Default Value: 00h Access: RO Size: 8 bits The IGD does not support the programmability of the master latency timer because it does not perform bursts. Bit Access & Default Description 7:0 RO 00h Master Latency Timer Count Value (MLTCV): Hardwired to 0s. |
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