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82G33 Datasheet(PDF) 245 Page - Intel Corporation |
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82G33 Datasheet(HTML) 245 Page - Intel Corporation |
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245 / 437 page  Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) Datasheet 245 Bit Access & Default Description 5 RO 0b Video Palette Snooping (VPS): This bit is hardwired to 0 to disable snooping. 4 RO 0b Memory Write and Invalidate Enable (MWIE): Hardwired to 0. The IGD does not support memory write and invalidate commands. 3 RO 0b Special Cycle Enable (SCE): This bit is hardwired to 0. The IGD ignores Special cycles. 2 RW 0b Bus Master Enable (BME): This bit controls the IGD's response to bus master accesses. 0 = Disable IGD bus mastering. 1 = Enable the IGD to function as a PCI compliant master. 1 RW 0b Memory Access Enable (MAE): This bit controls the IGD's response to memory space accesses. 0 = Disable. 1 = Enable. 0 RW 0b I/O Access Enable (IOAE): This bit controls the IGD's response to I/O space accesses. 0 = Disable. 1 = Enable. |
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