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82G33 Datasheet(PDF) 244 Page - Intel Corporation

Part # 82G33
Description  Graphics and Memory Controller Hub
PDF  437 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82G33 Datasheet(HTML) 244 Page - Intel Corporation

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Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
244
Datasheet
8.1.2
DID—Device Identification
B/D/F/Type:
0/2/0/PCI
Address Offset:
02–03h
Default Value:
29C2h
Access:
RO
Size:
16 bits
This register combined with the Vendor Identification register uniquely identifies any
PCI device.
Bit
Access &
Default
Description
15:0
RO
29C2h
Device Identification Number (DID): This is a 16 bit value assigned
to the GMCH Graphic device.
8.1.3
PCICMD2—PCI Command
B/D/F/Type:
0/2/0/PCI
Address Offset:
04–05h
Default Value:
0000h
Access:
RO, RW
Size:
16 bits
This 16-bit register provides basic control over the IGD's ability to respond to PCI
cycles. The PCICMD Register in the IGD disables the IGD PCI compliant master
accesses to main memory.
Bit
Access &
Default
Description
15:11
RO
00h
Reserved
10
RW
0b
Interrupt Disable (INTDIS): This bit disables the device from
asserting INTx#.
0 = Enable the assertion of this device's INTx# signal.
1 = Disable the assertion of this device's INTx# signal. DO_INTx
messages will not be sent to DMI.
9
RO
0b
Fast Back-to-Back (FB2B): Not Implemented. Hardwired to 0.
8
RO
0b
SERR Enable (SERRE): Not Implemented. Hardwired to 0.
7
RO
0b
Address/Data Stepping Enable (ADSTEP): Not Implemented.
Hardwired to 0.
6
RO
0b
Parity Error Enable (PERRE): Not Implemented. Hardwired to 0.
Since the IGD belongs to the category of devices that does not corrupt
programs or data in system memory or hard drives, the IGD ignores
any parity error that it detects and continues with normal operation.



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