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82G33 Datasheet(PDF) 240 Page - Intel Corporation |
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82G33 Datasheet(HTML) 240 Page - Intel Corporation |
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240 / 437 page  Direct Memory Interface (DMI) Registers 240 Datasheet 7.1.12 DMILCTL—DMI Link Control B/D/F/Type: 0/0/0/DMIBAR Address Offset: 88–89h Default Value: 0000h Access: RW, RO Size: 16 bits This register allows control of DMI. Bit Access & Default Description 15:8 RO 00h Reserved 7 RW 0b Extended Synch (EXTSYNC): 0 = Standard Fast Training Sequence (FTS). 1 = Forces the transmission of additional ordered sets when exiting the L0s state and when in the Recovery state. 6:3 RO 0h Reserved 2 RW 0b Far-End Digital Loopback (FEDLB): 1:0 RW 00b Active State Power Management Support (ASPMS): This field controls the level of active state power management supported on the given link. 00 = Disabled 01 = L0s Entry Supported 10 = Reserved 11 = L0s and L1 Entry Supported |
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