82G33 datasheet(239/437 Pages) INTEL

239 / 437 page

Direct Memory Interface (DMI) Registers

Datasheet

239

7.1.10

DMIVC1RSTS—DMI VC1 Resource Status

B/D/F/Type:

0/0/0/DMIBAR

Address Offset:

26–27h

Default Value:

0002h

Access:

Size:

16 bits

This register reports the Virtual Channel specific status.

Bit

Access &

Default

Description

15:2

0000h

Reserved

Virtual Channel 1 Negotiation Pending (VC1NP):

0 = The VC negotiation is complete.

1 = The VC resource is still in the process of negotiation (initialization

or disabling).

Reserved

7.1.11

DMILCAP—DMI Link Capabilities

B/D/F/Type:

0/0/0/DMIBAR

Address Offset:

84–87h

Default Value:

00012C41h

Access:

RO, RWO

Size:

32 bits

This register indicates DMI specific capabilities.

Bit

Access &

Default

Description

31:18

0000h

Reserved

17:15

RWO

010b

L1 Exit Latency (L1SELAT): This field indicates the length of time

this Port requires to complete the transition from L1 to L0.

010b = 2 us to less than 4 us.

14:12

RWO

010b

L0s Exit Latency (L0SELAT): This field indicates the length of time

this Port requires to complete the transition from L0s to L0.

010 = 128 ns to less than 256 ns

11:10

11b

Active State Link PM Support (ASLPMS): L0s & L1 entry

supported.

9:4

04h

Max Link Width (MLW): This field indicates the maximum number

of lanes supported for this link.

3:0

Max Link Speed (MLS): Hardwired to indicate 2.5 Gb/s.

82G33 Datasheet(PDF) 239 Page - Intel Corporation

82G33 Datasheet(HTML) 239 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL