82G33 datasheet(250/437 Pages) INTEL

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Integrated Graphics Device Registers (D2:F0,F1)

(Intel® 82Q35, 82Q33, 82G33 GMCH Only)

250

Datasheet

8.1.11

IOBAR—I/O Base Address

B/D/F/Type:

0/2/0/PCI

Address Offset:

14–17h

Default Value:

00000001h

Access:

RO, RW

Size:

32 bits

This register provides the Base offset of the I/O registers within Device 2. Bits 15:3

are programmable allowing the I/O Base to be located anywhere in 16 bit I/O Address

Space. Bits 2:1 are fixed and return zero; bit 0 is hardwired to a one indicating that 8

bytes of I/O space are decoded. Access to the 8Bs of I/O space is allowed in PM state

D0 when IO Enable (PCICMD bit 0) set. Access is disallowed in PM states D1–D3 or if

I/O Enable is clear or if Device 2 is turned off or if Internal graphics is disabled thru

the fuse or fuse override mechanisms.

Note that access to this IO BAR is independent of VGA functionality within Device 2.

Also note that this mechanism is available only through function 0 of Device 2 and is

not duplicated in function 1.

If accesses to this IO bar is allowed then the GMCH claims all 8, 16 or 32 bit I/O

cycles from the processor that falls within the 8B claimed.

Bit

Access &

Default

Description

31:16

0000h

Reserved

15:3

0000h

IO Base Address (IOBASE): Set by the OS, these bits correspond

to address signals 15:3.

2:1

00b

Memory Type (MEMTYPE): Hardwired to 0s to indicate 32-bit

address.

Memory/IO Space (MIOS): Hardwired to 1 to indicate I/O space.

8.1.12

SVID2—Subsystem Vendor Identification

B/D/F/Type:

0/2/0/PCI

Address Offset:

2C–2Dh

Default Value:

0000h

Access:

RWO

Size:

16 bits

Bit

Access &

Default

Description

15:0

RWO

0000h

Subsystem Vendor ID (SUBVID): This value is used to identify the

vendor of the subsystem. This register should be programmed by BIOS

during boot-up. Once written, this register becomes Read Only. This

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