82G33 datasheet(369/437 Pages) INTEL

369 / 437 page

Functional Description

Datasheet

369

10.8.3

Programming Sequence

The following sequence must be followed in BIOS to properly set up the Hot Trip Point

and ICH SMI# signal assertion:

1. In Thermal Sensor Control 1 Register (TSC1), set thermal sensor enable bit (TSE)

and the hysteresis value (DHA) by writing 99h to MCHBAR CD8h

2. Program the Hot Trip Point Register (TSTTP[HTPS]) by writing the appropriate

value to MCHBAR CDCh bits [15:8]

3. Program the Catastrophic Trip Point Setting Register (TSTTP[CTPS]) by writing

2Ch to MCHBAR CDCh bits [7:0]

4. In Thermal Sensor Control 2 Register (TSC2), program the Thermometer Mode

Enable and Rate (TE) by writing 04h to MCHBAR CD9h bits [3:0]

5. In the Hardware Protection Register (THERM1), program the Halt on Catastrophic

bit (HOC) by writing 08h to MCHBAR CE4h bits [7:0]

6. Lock the Hardware Protection by writing a 1 to the Lock bit (HTL) at MCHBAR

CE4h bit [0]

7. In Thermal SMI Command Register (TSMICMD), set the SMI# on Hot bit by

writing a 02h to MCHBAR CF1h

8. Program the SMI Command register (SMICMD[TSTSMI]) by writing a 1 to bit 11 to

PCI CCh

9. Program the TCO Register (TCO[TSLB]) to lock down the other register settings by

writing a 1 to bit 7 of MCHBAR CE2h

If the temperature rises above the Hot Trip point:

The TIS[Hot Thermal Sensor Interrupt Event] is set when SMI# interrupt is generated.

10. Clear this bit of the TIS register to allow subsequent interrupts of this type to get

registered.

11. Clear the global thermal sensor event bit in the Error Status Register, bit 11.

12.

13. In thermal sensor status register (TSS), the Hot trip indicator (HTI) bit is set if

this condition is still valid by the time the software gets to read the register.

82G33 Datasheet(PDF) 369 Page - Intel Corporation