82G33 datasheet(371/437 Pages) INTEL

371 / 437 page

Functional Description

Datasheet

371

10.9

Clocking

10.9.1

Overview

The (G)MCH has a total of 5 PLLs providing many times that many internal clocks. The

PLLs are:

• Host PLL – Generates the main core clocks in the host clock domain. Can also be

used to generate memory and internal graphics core clocks. Uses the Host clock

(H_CLKIN) as a reference.

• Memory IO PLL - Optionally generates low jitter clocks for memory IO interface, as

opposed to from Host PLL. Uses the Host FSB differential clock

(HPL_CLKINP/HPL_CLKINN) as a reference. Low jitter clock source from Memory

I/O PLL is required for DDR667 and higher frequencies.

• PCI Express PLL – Generates all PCI Express related clocks, including the Direct

Media Interface that connects to the ICH. This PLL uses the 100 MHz clock

(G_CLKIN) as a reference.

• Display PLL A – Generates the internal clocks for Display A. Uses D_REFCLKIN as a

reference.

• Display PLL B – Generates the internal clocks for Display B. Also uses D_REFCLKIN

as a reference.

• CK505 is the Clocking chip required for the Intel® 3 Series Express Chipset

platform

82G33 Datasheet(PDF) 371 Page - Intel Corporation