W97AH6KB datasheet(34/127 Pages) WINBOND

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W97AH6KB / W97AH2KB

Publication Release Date: May 15, 2014

Revision: A01-001

- 34 -

7.4.4

Reads Interrupted by a Read

For LPDDR2-S4 device, burst read can be interrupted by another read on even clock cycles after the Read

command, provided that tCCD is met.

7.4.4.1

Read Burst Interrupt Example: RL = 3, BL= 8, tCCD = 2

RL = 3

tCCD=2

Nop

Read

Nop

Col Addr A

DOUT A0

Bank N

Col Addr A

Read

Bank N

Col Addr B Col Addr B

CA0-9

[Cmd]

DQS

CK_t / CK_c

DQS_c

DQS_t

DOUT A1

DOUT A2 DOUT A3

DOUT B0 DOUT B1

DOUT B2 DOUT B3

DOUT B4 DOUT B5

Notes:

1. For LPDDR2-S4 devices, read burst interrupt function is only allowed on burst of 8 and burst of 16.

2. For LPDDR2-S4 devices, read burst interrupt may occur on any clock cycle after the intial read command, provided that tCCD is met.

3. Reads can only be interrupted by other reads or the BST command.

4. Read burst interruption is allowed to any bank inside DRAM.

5. Read burst with Auto-Precharge is not allowed to be interrupted.

6. The effective burst length of the first read equals two times the number of clock cycles between the first read and the interrupting read.

7.4.5

Burst Write Operation

The Burst Write command is initiated by having CS_n LOW, CA0 HIGH, CA1 LOW and CA2 LOW at the rising edge

of the clock. The command address bus inputs, CA5r-CA6r and CA1f-CA9f, determine the starting column address

for the burst. The Write Latency (WL) is defined from the rising edge of the clock on which the Write Command is

issued to the rising edge of the clock from which the tDQSS delay is measured. The first valid data must be driven WL

* tCK + tDQSS from the rising edge of the clock from which the Write command is issued. The data strobe signal

(DQS) should be driven LOW tWPRE prior to the data input. The data bits of the burst cycle must be applied to the

DQ pins tDS prior to the respective edge of the DQS_t, DQS_c and held valid until tDH after that edge. The burst data

are sampled on successive edges of the DQS_t, DQS_c until the burst length is completed, which is 4, 8, or 16 bit

burst.

For LPDDR2-SDRAM devices, tWR must be satisfied before a precharge command to the same bank may be issued

after a burst write operation.

Input timings are measured relative to the crosspoint of DQS_t and its complement, DQS_c.

W97AH6KB Datasheet(PDF) 34 Page - Winbond

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