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W97AH6KB Datasheet(PDF) 22 Page - Winbond |
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W97AH6KB Datasheet(HTML) 22 Page - Winbond |
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22 / 127 page  W97AH6KB / W97AH2KB Publication Release Date: May 15, 2014 Revision: A01-001 - 22 - 7.3.4 MR2_Device Feature 2 (MA[7:0] = 02H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 (RFU) RL & WL RL & WL Write-only OP[3:0] 0001b: RL = 3 / WL = 1 (default) 0010b: RL = 4 / WL = 2 0011b: RL = 5 / WL = 2 0100b: RL = 6 / WL = 3 0101b: RL = 7 / WL = 4 0110b: RL = 8 / WL = 4 All others: reserved 7.3.5 MR3_I/O Configuration 1 (MA[7:0] = 03H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 (RFU) DS DS Write-only OP[3:0] 0000b: reserved 0001b: 34.3-ohm typical 0010b: 40-ohm typical (default) 0011b: 48-ohm typical 0100b: 60-ohm typical 0101b: reserved 0110b: 80-ohm typical 0111b: 120-ohm typical All others: reserved 7.3.6 MR4_Device Temperature (MA[7:0] = 04H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 TUF (RFU) SDRAM Refresh Rate SDRAM Refresh Rate Read-only OP[2:0] 000b: SDRAM Low temperature operating limit exceeded 001b: 4x tREFI, 4x tREFIpb, 4x tREFW 010b: 2x tREFI, 2x tREFIpb, 2x tREFW 011b: 1x tREFI, 1x tREFIpb, 1x tREFW (≤ 85°C) 100b: Reserved 101b: 0.25x tREFI, 0.25x tREFIpb, 0.25x tREFW, do not de-rate SDRAM AC timing 110b: 0.25x tREFI, 0.25x tREFIpb, 0.25x tREFW, de-rate SDRAM AC timing 111b: SDRAM High temperature operating limit exceeded Temperature Update Flag (TUF) Read-only OP7 0b: OP[2:0] value has not changed since last read of MR4. 1b: OP[2:0] value has changed since last read of MR4. Notes: 1. A Mode Register Read from MR4 will reset OP7 to ‘0’. 2. OP7 is reset to ‘0’ at power-up. 3. If OP2 equals ‘1’, the device temperature is greater than 85°C. 4. OP7 is set to ‘1’ if OP2:OP0 has changed at any time since the last read of MR4. 5. LPDDR2 might not operate properly when OP[2:0] = 000b or 111b. 6. For specified operating temperature range and maximum operating temperature, refer to “Operating Temperature Conditions” table. 7. LPDDR2 devices must be derated by adding 1.875 nS to the following core timing parameters: tRCD, tRC, tRAS, tRP, and tRRD. tDQSCK shall be de-rated according to the tDQSCK de-rating value in “LPDDR2 AC Timing” table. Prevailing clock frequency spec and related setup and hold timings shall remain unchanged. 8. The recommended frequency for reading MR4 is provided in “Temperature Sensor” section. |
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