W97AH6KB datasheet(65/127 Pages) WINBOND

65 / 127 page

W97AH6KB / W97AH2KB

Publication Release Date: May 15, 2014

Revision: A01-001

- 65 -

7.4.24.5 ZQ External Resistor Value, Tolerance, and Capacitive Loading

To use the ZQ Calibration function, a 240 Ohm ± 1% tolerance external resistor must be connected between the ZQ

pin and ground. A single resistor can be used for each LPDDR2 device or one resistor can be shared between

multiple LPDDR2 devices if the ZQ calibration timings for each LPDDR2 device do not overlap. The total capacitive

loading on the ZQ pin must be limited (See section 8.2.6.7

“Input/Output Capacitance” table).

7.4.25 Power-Down

For LPDDR2 SDRAM, power-down is synchronously entered when CKE is registered LOW and CS_n HIGH at the

rising edge of clock. CKE must be registered HIGH in the previous clock cycle. A NOP command must be driven in

the clock cycle following the power-down command. CKE is not allowed to go LOW while mode register, read, or

write operations are in progress. CKE is allowed to go LOW while any of other operations such as row activation,

preactive, precharge, autoprecharge, or refresh is in progress, but power-down IDD spec will not be applied until

finishing those operations. Timing diagrams are shown in the following pages with details for entry into power down.

For LPDDR2 SDRAM, if power-down occurs when all banks are idle, this mode is referred to as idle power- down; if

power-down occurs when there is a row active in any bank, this mode is referred to as active power-down.

Entering power-down deactivates the input and output buffers, excluding CK_t, CK_c, and CKE. In power-down

mode, CKE must be maintained LOW while all other input signals are “Don’t Care”. CKE LOW must be maintained

until tCKE has been satisfied. VREF must be maintained at a valid level during power down.

VDDQ may be turned off during power down. If VDDQ is turned off, then VREFDQ must also be turned off. Prior to

exiting power down, both VDDQ and VREFDQ must be within their respective min/max operating ranges (See 8.2.1.1

“Recommended DC Operating Conditions” table).

For LPDDR2 SDRAM, the maximum duration in power-down mode is only limited by the refresh requirements

outlined in section 7.4.16

“LPDDR2 SDRAM Refresh Requirements”, as no refresh operations are performed in

power-down mode.

The power-down state is exited when CKE is registered HIGH. The controller shall drive CS_n HIGH in conjunction

with CKE HIGH when exiting the power-down state. CKE HIGH must be maintained until tCKE has been satisfied. A

valid, executable command can be applied with power-down exit latency, tXP after CKE goes HIGH. Power-down exit

latency is defined in section 8.7.1

“LPDDR2 AC Timing” table.

7.4.25.1 Basic Power Down Entry and Exit Timing

tCK (min)

tIHCKE

tCKE(min)

tISCKE

tIHCKE

Valid

Enter

NOP

Valid

Exit

Input clock frequency may be changed

or the input clock stopped during Power-Down

Enter Power-Down mode

Exit Power-Down mode

tXP(min)

tISCKE

CKE

[CMD]

CK_c

CK_t

CS_n

tcKE(min)

Valid

NOP

Note:

Input clock frequency may be changed or the input clock stopped during power-down, provided that upon exiting power-down, the clock is stable

and within specified limits for a minmum of 2 clock cycles prior to power-down exit and the clock frequency is between the minimum and maximum

frequency for the particular speed grade.

W97AH6KB Datasheet(PDF) 65 Page - Winbond

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