W97AH6KB datasheet(54/127 Pages) WINBOND

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W97AH6KB / W97AH2KB

Publication Release Date: May 15, 2014

Revision: A01-001

- 54 -

For LPDDR2 SDRAM, the maximum duration in power-down mode is only limited by the refresh requirements

outlined in section 7.4.16

“LPDDR2 SDRAM Refresh Requirements”, since no refresh operations are performed in

power-down mode.

2 tCK(min)

tIHCKE

tCKESR(min)

tISCKE

tIHCKE

Valid

Enter SR

NOP

Valid

Exit SR

Input clock frequency may be changed

or stopped during Self-Refresh

Enter Self-Refresh

Exit Self-Refresh

tXSR(min)

tISCKE

CKE

[Cmd]

CK_c

CK_t

CS_n

Figure of Self Refresh Operation

Notes:

1. Input clock frequency may be changed or stopped during self-refresh, provided that upon exiting self-refresh, a minimum of 2 clocks of stable

clock are provided and the clock frequency is between the minimum and maximum frequency for the particular speed grad

Device must be in the “All banks idle” state prior to entering Self Refresh mode.

3. tXSR begins at the rising edge of the clock after CKE is driven HIGH.

4. A valid command may be issued only after tXSR is satisfied. NOPs shall be issued during tXSR.

7.4.18 Partial Array Self-Refresh: Bank Masking

Each bank of LPDDR2 SDRAM can be independently configured whether a self refresh operation is taking place.

One mode register unit of 8 bits accessible via MRW command is assigned to program the bank masking status of

each bank up to 8 banks. For bank masking bit assignments, see section 7.3.13 Mode Register 16

“MR16_PASR_Bank Mask (MA[7:0] = 10H)”.

The mask bit to the bank controls a refresh operation of entire memory within the bank. If a bank is masked via MRW,

a refresh operation to the entire bank is blocked and data retention by a bank is not guaranteed in self refresh mode.

To enable a refresh operation to

a bank, a coupled mask bit has to be programmed, “unmasked”. When a bank mask

bit is unmasked, a refresh to a bank is determined by the programmed status of segment mask bits.

7.4.19 Partial Array Self-Refresh: Segment Masking

Segment masking scheme may be used in place of or in combination with bank masking scheme in LPDDR2-S4

SDRAM. The number of segments differ by the density and the setting of each segment mask bit is applied across

all the banks. For segment masking bit assignments, see section 7.3.14 Mode Register 17

“MR17_PASR_Segment

Mask (MA[7:0] = 11H)

”.

For those refresh-enabled banks, a refresh operation to the address range which is represented by a segment is

blocked when the mask bit to this segment is programmed, “masked”. Programming of segment mask bits is similar

to the one of bank mask bits.

W97AH6KB Datasheet(PDF) 54 Page - Winbond

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