 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
W97AH6KB Datasheet(PDF) 17 Page - Winbond |
|
|
|||||||||||||||||||||||||||||
W97AH6KB Datasheet(HTML) 17 Page - Winbond |
|
|
17 / 127 page  W97AH6KB / W97AH2KB Publication Release Date: May 15, 2014 Revision: A01-001 - 17 - 7.2.2 Timing Parameters for Initialization Symbol Value Unit Comment min max tINIT0 20 mS Maximum Power Ramp Time tINIT1 100 nS Minimum CKE low time after completion of power ramp tINIT2 5 tCK Minimum stable clock before first CKE high tINIT3 200 µS Minimum Idle time after first CKE assertion tINIT4 1 µS Minimum Idle time after Reset command tINIT5 10 µS Maximum duration of Device Auto-Initialization tZQINIT 1 µS ZQ Initial Calibration for LPDDR2-S4 tCKb 18 100 nS Clock cycle time during boot 7.2.3 Power Ramp and Initialization Sequence *Midlevel on CA bus means : valid NOP tINIT2 = 5 tCK (min) tINIT3 = 200 μs (min) tINIT1 = 100 ns (min) tINIT0 = 20 ms (max) tINIT4 = 1 μs (min) tISCKE tINIT5 Ta Tb Tc Tg Te Td RESET ZQC Valid CK_t / CK_c Supplies CKE CA* DQ PD Tf MRR tZQINIT |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
