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W97AH6KB Datasheet(PDF) 24 Page - Winbond |
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W97AH6KB Datasheet(HTML) 24 Page - Winbond |
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24 / 127 page  W97AH6KB / W97AH2KB Publication Release Date: May 15, 2014 Revision: A01-001 - 24 - 7.3.12 MR10_Calibration (MA[7:0] = 0AH) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Calibration Code Calibration Code Write-only OP[7:0] 0xFF: Calibration command after initialization 0xAB: Long calibration 0x56: Short calibration 0xC3: ZQ Reset others: Reserved Notes: 1. Host processor shall not write MR10 with “Reserved” values. 2. LPDDR2 devices shall ignore calibration command when a “Reserved” value is written into MR10. 3. See AC timing table for the calibration latency. 4. If ZQ is connected to VSSCA through RZQ, either the ZQ calibration function (see section 7.4.24 “Mode Register Write ZQ Calibration Command ”) or default calibration (through the ZQreset command) is supported. If ZQ is connected to VDDCA, the device operates with default calibration, and ZQ calibration commands are ignored. In both cases, the ZQ connection shall not change after power is applied to the device. 5. Optionally, the MRW ZQ Initialization Calibration command will update MR0 to indicate RZQ pin connection. 7.3.13 MR16_PASR_Bank Mask (MA[7:0] = 10H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 S4 SDRAM Bank Mask (8-bank) Bank [7:0] Mask Write-only OP[7:0] 0b: refresh enable to the bank (=unmasked, default) 1b: refresh blocked (=masked) OP Bank Mask 8-Bank S4 SDRAM 0 XXXXXXX1 Bank 0 1 XXXXXX1X Bank 1 2 XXXXX1XX Bank 2 3 XXXX1XXX Bank 3 4 XXX1XXXX Bank 4 5 XX1XXXXX Bank 5 6 X1XXXXXX Bank 6 7 1XXXXXXX Bank 7 |
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