W97AH6KB datasheet(10/127 Pages) WINBOND

10 / 127 page

W97AH6KB / W97AH2KB

Publication Release Date: May 15, 2014

Revision: A01-001

- 10 -

PIN DESCRIPTION

5.1

Basic Functionality

Name

Type

Description

CK_t, CK_c

Input

Clock: CK_t and CK_c are differential clock inputs. All Double Data Rate (DDR) CA inputs are sampled on both

positive and negative edge of CK_t. Single Data Rate (SDR) inputs, CS_n and CKE, are sampled at the positive

Clock edge.

Clock is defined as the differential pair, CK_t and CK_c. The positive Clock edge is defined by the crosspoint of a

rising CK_t and a falling CK_c. The negative Clock edge is defined by the crosspoint of a falling CK_t and a rising

CK_c.

CKE

Input

Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and therefore device input

buffers and output drivers. Power savings modes are entered and exited through CKE transitions.

CKE is considered part of the command code. See 7.5.1

“Command Truth Table” for command code

descriptions.

CKE is sampled at the positive Clock edge.

CS_n

Input

Chip Select: CS_n is considered part of the command code. See 7.5.1 “Command Truth Table” for

command code descriptions.

CS_n is sampled at the positive Clock edge.

CA[n:0]

Input

DDR Command/Address Inputs: Uni-directional command/address bus inputs.

CA is considered part of the command code. See 7.5.1

“Command Truth Table” for command code

descriptions.

DQ[n:0]

I/O

Data Inputs/Output: Bi-directional data bus. n=15 for 16 bits DQ; n=31 for 32 bits DQ.

DQSn_t,

DQSn_c

I/O

Data Strobe (Bi-directional, Differential):

The data strobe is bi-directional (used for read and write data) and differential (DQS_t and DQS_c). It is output

with read data and input with write data. DQS_t is edge-aligned to read data and centered with write data.

For x16, DQS0_t and DQS0_c correspond to the data on DQ0-7; DQS1_t and DQS1_c to the data on DQ8-15.

For x32 DQS0_t and DQS0_c correspond to the data on DQ0-7; DQS1_t and DQS1_c to the data on DQ8-15;

DQS2_t and DQS2_c to the data on DQ16-23; DQS3_t and DQS3_c to the data on DQ24-31.

DMn

Input

Input Data Mask:

DM is the input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that

input data during a Write access. DM is sampled on both edges of DQS_t. Although DM is for input only, the DM

loading shall match the DQ and DQS (or DQS_c).

DM0 is the input data mask signal for the data on DQ0-7.

For x16 and x32 devices, DM1 is the input data mask signal for the data on DQ8-15.

For x32 devices, DM2 is the input data mask signal for the data on DQ16-23 and DM3 is the input data mask

signal for the data on DQ24-31.

VDD1

Supply

Core Power Supply 1: Power supply for core

VDD2

Supply

Core Power Supply 2: Power supply for core.

VDDCA

Supply

Input Receiver Power Supply: Power supply for CA[n:0], CKE, CS_n, CK_t, and CK_c input buffers.

VDDQ

Supply

I/O Power Supply: Power supply for Data input/output buffers.

VREF(CA)

Supply

Reference Voltage for CA Command and Control Input Receiver: Reference voltage for all

CA[n:0], CKE, CS_n, CK_t, and CK_c input buffers.

VREF(DQ)

Supply

Reference Voltage for DQ Input Receiver: Reference voltage for all Data input buffers.

VSS

Supply

Ground

VSSCA

Supply

Ground for CA Input Receivers

VSSQ

Supply

I/O Ground

I/O

Reference Pin for Output Drive Strength Calibration

Note: Data includes DQ and DM.

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