W97AH6KB datasheet(72/127 Pages) WINBOND

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W97AH6KB / W97AH2KB

Publication Release Date: May 15, 2014

Revision: A01-001

- 72 -

LPDDR2 devices support clock stop during CKE LOW under the following conditions:

• CK_t is held LOW and CK_c is held HIGH during clock stop;

• Refresh Requirements apply during clock stop;

• During clock stop, only REFab or REFpb commands may be executing;

• Any Activate, or Precharge commands have executed to completion prior to stopping the clock;

• The related timing conditions (tRCD, tRP) have been met prior to stopping the clock;

• The initial clock frequency shall be maintained for a minimum of 2 clock cycles after CKE goes LOW;

• The clock satisfies tCH(abs) and tCL(abs) for a minimum of 2 clock cycles prior to CKE going HIGH.

LPDDR2 devices support input clock frequency change during CKE HIGH under the following conditions:

• tCK(abs)min is met for each clock cycle;

• Refresh Requirements apply during clock frequency change;

• Any Activate, Read, Write, Precharge, Mode Register Write, or Mode Register Read commands must have

executed to completion, including any associated data bursts prior to changing the frequency;

• The related timing conditions (tRCD, tWR, tWRA, tRP, tMRW, tMRR, etc.) have been met prior to changing the

frequency;

• CS_n shall be held HIGH during clock frequency change;

• During clock frequency change, only REFab or REFpb commands may be executing;

• The LPDDR2 device is ready for normal operation after the clock satisfies tCH(abs) and tCL(abs) for a minimum of

2tCK + tXP.

After the input clock frequency is changed, additional MRW commands may be required to set the WR, RL etc.

These settings may need to be adjusted to meet minimum timing requirements at the target clock frequency.

LPDDR2 devices support clock stop during CKE HIGH under the following conditions:

• CK_t is held LOW and CK_c is held HIGH during clock stop;

• CS_n shall be held HIGH during clock clock stop;

• Refresh Requirements apply during clock stop;

• During clock stop, only REFab or REFpb commands may be executing;

• Any Activate, Read, Write, Precharge, Mode Register Write, or Mode Register Read commands must have

executed to completion, including any associated data bursts prior to stopping the clock;

• The related timing conditions (tRCD, tWR, tWRA, tRP, tMRW, tMRR, etc.) have been met prior to stopping the clock;

• The LPDDR2 device is ready for normal operation after the clock is restarted and satisfies tCH(abs) and tCL(abs) for a

minimum of 2tCK + tXP.

7.4.28 No Operation Command

The purpose of the No Operation command (NOP) is to prevent the LPDDR2 device from registering any unwanted

command between operations. Only when the CKE level is constant for clock cycle N-1 and clock cycle N, a NOP

command may be issued at clock cycle N. A NOP command has two possible encodings:

1. CS_n HIGH at the clock rising edge N.

2. CS_n LOW and CA0, CA1, CA2 HIGH at the clock rising edge N.

The No Operation command will not terminate a previous operation that is still executing, such as a burst read or

write cycle.

7.5

Truth Tables

The truth tables provide complementary information to the state diagram, they clarify the device behavior and the

applied restrictions when considering the actual state of all the Banks.

Operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation, the

LPDDR2 device must be powered down and then restarted through the specified initialization sequence before

normal operation can continue.

W97AH6KB Datasheet(PDF) 72 Page - Winbond

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