W97AH6KB datasheet(53/127 Pages) WINBOND

53 / 127 page

W97AH6KB / W97AH2KB

Publication Release Date: May 15, 2014

Revision: A01-001

- 53 -

7.4.17 Self Refresh Operation

The Self Refresh command can be used to retain data in the LPDDR2 SDRAM, even if the rest of the system is

powered down. When in the Self Refresh mode, the LPDDR2 SDRAM retains data without external clocking. The

LPDDR2 SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is

defined by having CKE LOW, CS_n LOW, CA0 LOW, CA1 LOW, and CA2 HIGH at the rising edge of the clock. CKE

must be HIGH during the previous clock cycle. A NOP command must be driven in the clock cycle following the

power-down command. Once the command is registered, CKE must be held LOW to keep the device in Self Refresh

mode.

LPDDR2-S4 devices can operate in Self Refresh in both the Standard or Extended Temperature Ranges. LPDDR2-

S4 devices will also manage Self Refresh power consumption when the operating temperature changes, lower at low

temperatures and higher temperatures.

Once the LPDDR2 SDRAM has entered Self Refresh mode, all of the external signals except CKE, are “don’t care”.

For proper self refresh operation, power supply pins (VDD1, VDD2, and VDDCA) must be at valid levels. VDDQ may be

turned off during Self-Refresh. Prior to exiting Self-Refresh, VDDQ must be within specified limits. VrefDQ and VrefCA

may be at any level within minimum and maximum levels (see section 8.1

“Absolute Maximum DC Ratings” table).

However prior to exit Self-Refresh, VrefDQ and VrefCA must be within specified limits (see section 8.2.1.1

“Recommended DC Operating Conditions” table). The SDRAM initiates a minimum of one all-bank refresh

command internally within tCKESR period once it enters Self Refresh mode. The clock is internally disabled during

Self Refresh Operation to save power. The minimum time that the LPDDR2 SDRAM must remain in Self Refresh

mode is tCKESR. The user may change the external clock frequency or halt the external clock one clock after Self

Refresh entry is registered; however, the clock must be restarted and stable before the device can exit Self Refresh

operation.

The procedure for exiting Self Refresh requires a sequence of commands. First, the clock shall be stable and within

specified limits for a minmum of 2 clock cycles prior to CKE going back HIGH. Once Self Refresh Exit is registered, a

delay of at least tXSR must be satisfied before a valid command can be issued to the device to allow for any internal

refresh in progress. CKE must remain HIGH for the entire Self Refresh exit period tXSR for proper operation except

for self refresh re-entry. NOP commands must be registered on each positive clock edge during the Self Refresh exit

interval tXSR.

The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be missed when

CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh, it is required that at least one Refresh

command (8 per-bank or 1 all-bank) is issued before entry into a subsequent Self Refresh.

W97AH6KB Datasheet(PDF) 53 Page - Winbond