W97AH6KB datasheet(82/127 Pages) WINBOND

82 / 127 page

W97AH6KB / W97AH2KB

Publication Release Date: May 15, 2014

Revision: A01-001

- 82 -

8.2.4.2.1

VRef(DC) Tolerance and VRef AC-Noise Limits

VRef ac-noise

VRef (DC)max

VRef (DC)min

VRef (t)

VDD

VSS

VRef (DC)

voltage

time

VDD/2

The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VRef.

“VRef” shall be understood as VRef(DC), as defined in above “VRef(DC) Tolerance and VRef AC-Noise Limits”

figure.

This clarifies that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid high or low

level and therefore the time to which setup and hold is measured. Devices will function correctly with appropriate

timing deratings with VREF outside these specified levels so long as VREF is maintained between 0.44 x VDDQ (or

VDDCA) and 0.56 x VDDQ (or VDDCA) and so long as the controller achieves the required single-ended AC and DC

input levels from instantaneous VRef (see 8.2.4.1.1

“Single-Ended AC and DC Input Levels for CA and CS_n

Inputs

” table and 8.2.4.1.3 “Single-Ended AC and DC Input Levels for DQ and DM” table) Therefore, system

timing and voltage budgets need to account for VREF deviations outside of this range.

This also clarifies that the LPDDR2 setup/hold specification and derating values need to include time and voltage

associated with VRef ac-noise. Timing and voltage effects due to ac-noise on VRef up to the specified limit (± 1% of

VDD) are included in LPDDR2 timings and their associated deratings.

W97AH6KB Datasheet(PDF) 82 Page - Winbond