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W97AH6KB Datasheet(PDF) 14 Page - Winbond |
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W97AH6KB Datasheet(HTML) 14 Page - Winbond |
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14 / 127 page  W97AH6KB / W97AH2KB Publication Release Date: May 15, 2014 Revision: A01-001 - 14 - 7.1.1 Simplified LPDDR2 Bus Interface State Diagram Precharging Writing With Autoprecharge Reading With Autoprecharge Reading Writing Active*1 Active Power Down Active MR Reading MR Writing Idle Power Down Idle Idle MR Reading Resetting Refreshing Self Refreshing Deep Power Down Power On Resetting MR Reading Resetting Power Down Automatic Sequence Command Sequence Power Applied Reset MRR PD PDX BST WR WRA WRA WR PD PDX Reset DPDX MRR MRW MRR PD PDX RD RD BST DPD SREF SREFX REF ACT RDA RDA PR,PRA PR(A)=Precharge (All) ACT=Activate WR(A)=Write(with Autoprecharge) RD(A)=Read (with Autoprecharge) BST=Burst Terminate Reset=Reset is achieved through MRW command MRW=Mode Register Write MRR=Mode Register Read PD=Enter Power Down PDX=Exit Power Down SREF=Enter Self Refresh SREFX=Exit Self Refresh DPD=Enter Deep Power Down DPDX=Exit Deep Power Down REF=Refresh PR,PRA Note: For LPDDR2-SDRAM in the Idle state, all banks are precharged. |
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