W97AH6KB datasheet(16/127 Pages) WINBOND

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W97AH6KB / W97AH2KB

Publication Release Date: May 15, 2014

Revision: A01-001

- 16 -

3. Reset command

After tINIT3 is satisfied, a MRW(Reset) command shall be issued (Td). The memory controller may optionally issue a

Precharge-All command prior to the MRW Reset command. Wait for at least tINIT4 = 1 µS while keeping CKE

asserted and issuing NOP commands.

4. Mode Registers Reads and Device Auto-Initialization (DAI) polling:

After tINIT4 is satisfied (Te) only MRR commands and power-down entry/exit commands are allowed. Therefore, after

Te, CKE may go low in accordance to Power-Down entry and exit specification (see section 7.4.25

“Power-Down”).

The MRR command may be used to poll the DAI-bit to acknowledge when Device Auto-Initialization is complete or

the memory controller shall wait a minimum of tINIT5 before proceeding.

As the memory output buffers are not properly configured yet, some AC parameters may have relaxed timings before

the system is appropriately configured.

After the DAI-

bit (MR#0, “DAI”) is set to zero “DAI complete” by the memory device, the device is in idle state (Tf).

The state of the DAI status bit can be determined by an MRR command to MR#0.

The LPDDR2 SDRAM device will set the DAI-bit no later than tINIT5 (10 µS) after the Reset command. The memory

controller shall wait a minimum of tINIT5 or until the DAI-bit is set before proceeding.

After the DAI-Bit is set, it is recommended to determine the device type and other device characteristics by issuing

MRR commands (MR0 “Device Information” etc.).

5. ZQ Calibration:

After tINIT5 (Tf), an MRW ZQ Initialization Calibration command may be issued to the memory (MR10). This

command is used to calibrate the LPDDR2 output drivers (RON) over process, voltage, and temperature. Optionally,

the MRW ZQ Initialization Calibration command will update MR0 to indicate RZQ pin connection. In systems in which

more than one LPDDR2 device exists on the same bus, the controller must not overlap ZQ Calibration commands.

The device is ready for normal operation after tZQINIT.

6. Normal Operation:

After tZQINIT (Tg), MRW commands may be used to properly configure the memory, for example the output buffer

driver strength, latencies etc. Specifically, MR1, MR2, and MR3 shall be set to configure the memory for the target

frequency and memory configuration.

The LPDDR2 device will now be in IDLE state and ready for any valid command.

After Tg, the clock frequency may be changed according to the clock frequency change procedure described in

section 7.4.27

“Input Clock Stop and Frequency Change”.

W97AH6KB Datasheet(PDF) 16 Page - Winbond