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W97AH6KB Datasheet(PDF) 99 Page - Winbond

Part # W97AH6KB
Description  Four-bit prefetch DDR architecture
PDF  127 Pages
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Manufacturer  WINBOND [Winbond]
Direct Link  http://www.winbond.com
Logo WINBOND - Winbond

W97AH6KB Datasheet(HTML) 99 Page - Winbond

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W97AH6KB / W97AH2KB
Publication Release Date: May 15, 2014
Revision: A01-001
- 99 -
8.3.1.2
Definition of Switching for IDD4R
Clock
CKE
CS_n
Clock Cycle Number
Command
CA0-CA2
CA3-CA9
All DQ
Rising
HIGH
LOW
N
Read_Rising
HLH
LHLHLHL
L
Falling
HIGH
LOW
N
Read_Falling
LLL
LLLLLLL
L
Rising
HIGH
HIGH
N + 1
NOP
LLL
LLLLLLL
H
Falling
HIGH
HIGH
N + 1
NOP
HLH
HLHLLHL
L
Rising
HIGH
LOW
N + 2
Read_Rising
HLH
HLHLLHL
H
Falling
HIGH
LOW
N + 2
Read_Falling
LLL
HHHHHHH
H
Rising
HIGH
HIGH
N + 3
NOP
LLL
HHHHHHH
H
Falling
HIGH
HIGH
N + 3
NOP
HLH
LHLHLHL
L
Notes:
1. Data strobe (DQS) is changing between HIGH and LOW every clock cycle.
2. The above pattern (N, N+1...) is used continuously during IDD measurement for IDD4R.
8.3.1.3
Definition of Switching for IDD4W
Clock
CKE
CS_n
Clock Cycle Number
Command
CA0-CA2
CA3-CA9
All DQ
Rising
HIGH
LOW
N
Write_Rising
HLL
LHLHLHL
L
Falling
HIGH
LOW
N
Write_Falling
LLL
LLLLLLL
L
Rising
HIGH
HIGH
N + 1
NOP
LLL
LLLLLLL
H
Falling
HIGH
HIGH
N + 1
NOP
HLH
HLHLLHL
L
Rising
HIGH
LOW
N + 2
Write_Rising
HLL
HLHLLHL
H
Falling
HIGH
LOW
N + 2
Write_Falling
LLL
HHHHHHH
H
Rising
HIGH
HIGH
N + 3
NOP
LLL
HHHHHHH
H
Falling
HIGH
HIGH
N + 3
NOP
HLH
LHLHLHL
L
Notes:
1. Data strobe (DQS) is changing between HIGH and LOW every clock cycle.
2. Data masking (DM) must always be driven LOW.
3. The above pattern (N, N+1...) is used continuously during IDD measurement for IDD4W.



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