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W97AH6KB Datasheet(PDF) 102 Page - Winbond

Part # W97AH6KB
Description  Four-bit prefetch DDR architecture
PDF  127 Pages
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Manufacturer  WINBOND [Winbond]
Direct Link  http://www.winbond.com
Logo WINBOND - Winbond

W97AH6KB Datasheet(HTML) 102 Page - Winbond

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W97AH6KB / W97AH2KB
Publication Release Date: May 15, 2014
Revision: A01-001
- 102 -
8.3.2.2
IDD6 Partial Array Self-Refresh Current, -40°C~85°C (x16, x32)
Parameter
Symbol Power Supply
400 MHz
533 MHz
Condition
Unit
IDD6 Partial Array
Self-Refresh
Current
Full Array
IDD61
VDD1
900
900
Self refresh current
CK_t=LOW, CK_c=HIGH;
CKE is LOW;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
µA
IDD62
VDD2
2000
2000
IDD6IN
VDDCA
VDDQ
40
40
1/2 Array
IDD61
VDD1
800
800
µA
IDD62
VDD2
1500
1500
IDD6IN
VDDCA
VDDQ
40
40
1/4 Array
IDD61
VDD1
700
700
µA
IDD62
VDD2
1200
1200
IDD6IN
VDDCA
VDDQ
40
40
1/8 Array
IDD61
VDD1
650
650
µA
IDD62
VDD2
1000
1000
IDD6IN
VDDCA
VDDQ
40
40
Notes:
1. LPDDR2-S4 SDRAM uses the same PASR scheme & IDD6 current value categorization as LPDDR (JESD209).
2. LPDDR2-S4 SDRAM devices support both bank-masking & segment-masking. The IDD6 currents are measured using bank-masking only.
3. IDD values published are the maximum of the distribution of the arithmetic mean.
8.4
Clock Specification
The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max values may
result in malfunction of the LPDDR2 device.
8.4.1
Definition for tCK(avg) and nCK
tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock period
is calculated from rising edge to rising edge.
tCK(avg) =
N
j
j
tCK
1
/ N
where
N = 200
Unit ‘tCK(avg)’ represents the actual clock average tCK(avg) of the input clock under operation. Unit ‘nCK’ represents
one clock cycle of the input clock, counting the actual clock edges.
tCK(avg) may change by up to ± 1% within a 100 clock cycle window, provided that all jitter and timing specs are met.
8.4.2
Definition for tCK(abs)
tCK(abs) is defined as the absolute clock period, as measured from one rising edge to the next consecutive rising
edge.
tCK(abs) is not subject to production test.



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