W97AH6KB datasheet(36/127 Pages) WINBOND

36 / 127 page

W97AH6KB / W97AH2KB

Publication Release Date: May 15, 2014

Revision: A01-001

- 36 -

7.4.5.3

Burst Wirte Followed by Burst Read: RL = 3, WL= 1, BL= 4

CK_t / CK_c

CA0-9

[Cmd]

Nop

Read

Nop

Write

DQS_c

DQS

tWTR

Bank M

Col Addr A Col Addr A

DIN A0

DIN A1

DIN A2

DIN A3

WL = 1

Bank N

Col Addr B Col Addr B

RL = 3

DQS_t

Notes:

The minimum number of clock cycles from the burst write command to the burst read command for any bank is [WL + 1 + BL/2 +

RU( tWTR/tCK)].

tWTR starts at the rising edge of the clock after the last valid input datum.

If a write burst is truncated with a Burst Terminate (BST) command, the effective burst length of the truncated write burst should be

used as “BL” to calculate the minimum write to read delay.

7.4.5.4

Seamless Burst Write: WL= 1, BL = 4, tCCD = 2

CK_t / CK_c

CA0-9

[Cmd]

Nop

Write

Nop

Write

DQS_c

DQS

WL=1

Bank M

Col Addr A Col Addr A

DIN A0

DIN A1

DIN A2

DIN A3

tCCD = 2

Bank N

Col Addr B Col Addr B

DIN B0

DIN B1

DIN B2

DIN B3

DQS_t

Note:

The seamless burst write operation is supported by enabling a write command every other clock for BL = 4 operation, every four clocks for

BL = 8 operation, or every eight clocks for BL = 16 operation. This operation is allowed regardless of same or different banks as long as the

banks are activated

W97AH6KB Datasheet(PDF) 36 Page - Winbond

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