W97AH6KB datasheet(71/127 Pages) WINBOND

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W97AH6KB / W97AH2KB

Publication Release Date: May 15, 2014

Revision: A01-001

- 71 -

The contents of the SDRAM may be lost upon entry into Deep Power-Down mode.

The Deep Power-Down state is exited when CKE and CS_n are registered HIGH, while meeting tISCKE with a stable

clock input. The SDRAM must be fully re-initialized by controller as described in the Power up initialization

Sequence. The SDRAM is ready for normal operation after the initialization sequence.

7.4.26.1 Deep Power Down Entry and Exit Timing

tCK (min)

tDPD

tISCKE

tIHCKE

NOP

Enter

DPD

NOP

Reset

Exit

DPD

Input clock frequency may be changed

or the input clock stopped during Deep Power-Down

Enter Deep Power-Down mode

Exit Deep Power-Down mode

tISCKE

CKE

[Cmd]

CS_n

NOP

tINIT3 = 200 μs (min)

NOP

CK_c

CK_t

tRP

Notes:

1. Initialization sequence may start at any time after TC.

tINIT3 and TC refer to timings in the LPDDR2 initialization sequence. For more detail, see section 7.2 “Power-up, Initialization, and Power-

Off

”.

3. Input clock frequency may be changed or the input clock stopped during deep power-down, provided that upon exiting deep power-down, the

clock is stable and within specified limits for a minmum of 2 clock cycles prior to deep power-down exit and the clock frequency is between the

minimum and maximum frequency for the particular speed grade.

7.4.27 Input Clock Stop and Frequency Change

LPDDR2 devices support input clock frequency change during CKE LOW under the following conditions:

• tCK(abs)min is met for each clock cycle;

• Refresh Requirements apply during clock frequency change;

• During clock frequency change, only REFab or REFpb commands may be executing;

• Any Activate, or Precharge commands have executed to completion prior to changing the frequency;

• The related timing conditions (tRCD, tRP) have been met prior to changing the frequency;

• The initial clock frequency shall be maintained for a minimum of 2 clock cycles after CKE goes LOW;

• The clock satisfies tCH(abs) and tCL(abs) for a minimum of 2 clock cycles prior to CKE going HIGH.

After the input clock frequency is changed and CKE is held HIGH, additional MRW commands may be required to

set the WR, RL etc. These settings may need to be adjusted to meet minimum timing requirements at the target

clock frequency.

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