W97AH6KB datasheet(33/127 Pages) WINBOND

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W97AH6KB / W97AH2KB

Publication Release Date: May 15, 2014

Revision: A01-001

- 33 -

7.4.3.8

Burst Read Followed by Burst Write: RL = 3, WL = 1, BL = 4

CK_t / CK_c

CA0-9

[Cmd]

Nop

Write

Nop

Read

DQS_c

DQS

tDQSCK

RL = 3

Bank A

Col Addr

DOUT A0

DOUT A1

DOUT A2

DOUT A3

DIN A0

DIN A1

DIN A2

WL=1

tDQSSmin

BL / 2

Bank A

Col Addr

DQS_t

The minimum time from the burst read command to the burst write command is defined by the Read Latency (RL)

and the Burst Length (BL). Minimum read to write latency is RL + RU(tDQSCKmax/tCK) + BL/2 + 1 - WL clock cycles.

Note that if a read burst is truncated with a Burst Terminate (BST) command, the effective burst length of the

truncated read burst should be used as “BL” to calculate the minimum read to write delay.

7.4.3.9

Seamless Burst Read: RL = 3, BL= 4, tCCD = 2

CK_t / CK_c

CA0-9

[Cmd]

Nop

Read

Nop

Read

DQS_c

DQS

RL = 3

Bank N

Col Addr A Col Addr A

DOUT A0

tCCD = 2

Bank N

Col Addr B Col Addr B

DQS_t

DOUT A1

DOUT A2

DOUT A3

DOUT B0

DOUT B1

DOUT B2

DOUT B3

The seamless burst read operation is supported by enabling a read command at every other clock for BL = 4

operation, every 4 clocks for BL = 8 operation, and every 8 clocks for BL=16 operation.

For LPDDR2-SDRAM, this operation is allowed regardless of whether the accesses read the same or different banks

as long as the banks are activated.

W97AH6KB Datasheet(PDF) 33 Page - Winbond

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