W97AH6KB datasheet(61/127 Pages) WINBOND

61 / 127 page

W97AH6KB / W97AH2KB

Publication Release Date: May 15, 2014

Revision: A01-001

- 61 -

7.4.22 Mode Register Write Command

The Mode Register Write command is used to write configuration data to mode registers. The Mode Register Write

(MRW) command is initiated by having CS_n LOW, CA0 LOW, CA1 LOW, CA2 LOW, and CA3 LOW at the rising

edge of the clock. The mode register is selected by {CA1f-CA0f, CA9r-CA4r}. The data to be written to the mode

only registers shall have no impact on the functionality of the device.

For LPDDR2-S4 devices, the MRW may only be issued when all banks are in the idle precharge state. One method

of ensuring that the banks are in the idle precharge state is to issue a Precharge-All command.

7.4.22.1 Mode Register Write Timing Example: RL = 3, tMRW = 5

CMD not allowed

CA0-9

[Cmd]

CK_t / CK_c

Tx + 1

Tx + 2

Ty + 1

Ty + 2

MRW

ANY

MR Addr MR Data

MR Data

MR Addr

tMRW

Notes:

1. The Mode Register Write Command period is tMRW. No command (other than Nop) is allowed during this period.

2. At time Ty, the device is in the idle state.

7.4.22.2 Truth Table for Mode Register Read (MRR) and Mode Register Write (MRW)

Current State

Command

Intermediate State

Next State

All Banks Idle

MRR

Mode Register Reading (All Banks Idle)

All Banks Idle

MRW

Mode Register Writing (All Banks Idle)

All Banks Idle

MRW (RESET)

Resetting (Device Auto-Initialization)

All Banks Idle

Bank(s) Active

MRR

Mode Register Reading (Bank(s) Active)

Bank(s) Active

MRW

Not Allowed

MRW (RESET)

Not Allowed

W97AH6KB Datasheet(PDF) 61 Page - Winbond

W97AH6KB Datasheet(HTML) 61 Page - Winbond

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL