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W97AH6KB Datasheet(PDF) 90 Page - Winbond

Part # W97AH6KB
Description  Four-bit prefetch DDR architecture
PDF  127 Pages
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Manufacturer  WINBOND [Winbond]
Direct Link  http://www.winbond.com
Logo WINBOND - Winbond

W97AH6KB Datasheet(HTML) 90 Page - Winbond

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W97AH6KB / W97AH2KB
Publication Release Date: May 15, 2014
Revision: A01-001
- 90 -
8.2.5.4
Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and
measured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown in below table and figure.
Table of Differential Output Slew Rate Definition
Description
Measured
Defined by
from
to
Differential output slew rate for rising edge
VOLdiff(AC)
VOHdiff(AC)
[VOHdiff(AC) - VOLdiff(AC)] / DeltaTRdiff
Differential output slew rate for falling edge
VOHdiff(AC)
VOLdiff(AC)
[VOHdiff(AC) - VOLdiff(AC)] / DeltaTFdiff
Note: Output slew rate is verified by design and characterization, and may not be subject to production test.
Delta TFdiff
Delta TRdiff
0
VOLdiff(AC)
VOHdiff(AC)
Figure of Differential Output Slew Rate Definition
Table of Differential Output Slew Rate
Symbol
Parameter
LPDDR2-800/1066
Units
Min
Max
SRQdiff
Differential Output Slew Rate (RON = 40
Ω ± 30%)
3.0
7.0
V/nS
SRQdiff
Differential Output Slew Rate (RON = 60
Ω ± 30%)
2.0
5.0
V/nS
Description:
SR: Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
diff: differential Signals
Notes:
1. Measured with output reference load.
2. The output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and VOHdiff(AC).
3. Slew rates are measured under normal SSO conditions, with 1/2 of DQ signals per data byte driving logic-high and 1/2 of DQ signals per data
byte driving logic-low.



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