Electronic Components Datasheet Search
  English  ▼

X  

W97AH6KB Datasheet(PDF) 78 Page - Winbond

Part # W97AH6KB
Description  Four-bit prefetch DDR architecture
PDF  127 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  WINBOND [Winbond]
Direct Link  http://www.winbond.com
Logo WINBOND - Winbond

W97AH6KB Datasheet(HTML) 78 Page - Winbond

Back Button W97AH6KB Datasheet HTML 74Page - Winbond W97AH6KB Datasheet HTML 75Page - Winbond W97AH6KB Datasheet HTML 76Page - Winbond W97AH6KB Datasheet HTML 77Page - Winbond W97AH6KB Datasheet HTML 78Page - Winbond W97AH6KB Datasheet HTML 79Page - Winbond W97AH6KB Datasheet HTML 80Page - Winbond W97AH6KB Datasheet HTML 81Page - Winbond W97AH6KB Datasheet HTML 82Page - Winbond Next Button
Zoom Inzoom in Zoom Outzoom out
 78 / 127 page
background image
W97AH6KB / W97AH2KB
Publication Release Date: May 15, 2014
Revision: A01-001
- 78 -
4.
Refresh, Self-Refresh, and Mode Register Write commands may only be issued when all bank are idle.
5.
A Burst Terminate (BST) command cannot be issued to another bank; it applies to the bank represented by the current state only.
6.
The following states must not be interrupted by any executable command; NOP commands must be applied during each clock cycle while in
these states:
Idle MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been met, the bank
will be in the Idle state.
Resetting MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been met, the
bank will be in the Resetting state.
Active MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been met, the
bank will be in the Active state.
MR Writing: starts with the registration of a MRW command and ends when tMRW has been met. Once tMRW has been met, the bank will
be in the Idle state.
7.
tRRD must be met between Activate command to Bank n and a subsequent Activate command to Bank m.
8.
Reads or Writes listed in the Command column include Reads and Writes with Auto Precharge enabled and Reads and Writes with Auto
Precharge disabled.
9.
This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for pre- charging.
10. MRR is allowed during the Row Activating state (Row Activating starts with registration of an Activate command and ends when tRCD is met).
11. MRR is allowed during the Precharging state. (Precharging starts with registration of a Precharge command and ends when tRP is met.
12. Not bank-specific; requires that all banks are idle and no bursts are in progress.
13. The next state for Bank m depends on the current state of Bank m (Idle, Row Activating, Precharging, or Active). The reader shall note that
the state may be in transition when a MRR is issued. Therefore, if Bank m is in the Row Activating state and Precharging, the next state may
be Active and Precharge dependent upon tRCD and tRP respectively.
14. A Write command may be applied after the completion of the Read burst; otherwise a BST must be issued to end the Read prior to asserting a
Write command.
15. Read with auto precharge enabled or a Write with auto precharge enabled may be followed by any valid command to other banks provided
that the timing restrictions in 7.4.14.2
“Precharge & Auto Precharge Clarification” table are followed.
16. A Read command may be applied after the completion of the Write burst; otherwise, a BST must be issued to end the Write prior to asserting
a Read command.
17. Reset command is achieved through Mode Register Write command.
18. BST is allowed only if a Read or Write burst is ongoing.
7.5.5
Data Mask Truth Table
Name (Functional)
DM
DQs
Note
Write enable
L
Valid
1
Write inhibit
H
X
1
Note:
1.
Used to mask write data, provided coincident with the corresponding data.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com