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W97AH6KB Datasheet(PDF) 103 Page - Winbond

Part # W97AH6KB
Description  Four-bit prefetch DDR architecture
PDF  127 Pages
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Manufacturer  WINBOND [Winbond]
Direct Link  http://www.winbond.com
Logo WINBOND - Winbond

W97AH6KB Datasheet(HTML) 103 Page - Winbond

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W97AH6KB / W97AH2KB
Publication Release Date: May 15, 2014
Revision: A01-001
- 103 -
8.4.3
Definition for tCH(avg) and tCL(avg)
tCH(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses.
tCH(avg) =
N
j
j
tCH
1
/ (N × tCK(avg))
where
N = 200
tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses.
tCL(avg) =
N
j
j
tCL
1
/ (N × tCK(avg))
where
N = 200
8.4.4
Definition for tJIT(per)
tJIT(per) is the single period jitter defined as the largest deviation of any signal tCK from tCK(avg).
tJIT(per) = Min/max of {tCKi - tCK(avg) where i = 1 to 200}.
tJIT(per),act is the actual clock jitter for a given system.
tJIT(per),allowed is the specified allowed clock period jitter.
tJIT(per) is not subject to production test.
8.4.5
Definition for tJIT(cc)
tJIT(cc) is defined as the absolute difference in clock period between two consecutive clock cycles.
tJIT(cc) = Max of |{tCKi +1 - tCKi}|.
tJIT(cc) defines the cycle to cycle jitter.
tJIT(cc) is not subject to production test.
8.4.6
Definition for tERR(nper)
tERR(nper) is defined as the cumulative error across n multiple consecutive cycles from tCK(avg).
tERR(nper),act is the actual clock jitter over n cycles for a given system.
tERR(nper),allowed is the specified allowed clock period jitter over n cycles.
tERR(nper) is not subject to production test.
tERR(nper) =

1
n
i
i
j
j
tCK
– n × tCK(avg)
tERR(nper),min can be calculated by the formula shown below:
tERR(nper), min = (1 + 0.68LN(n)) × tJIT(per), min
tERR(nper),max can be calculated by the formula shown below:
tERR(nper), max = (1 + 0.68LN(n)) × tJIT(per), max
Using these equations, tERR(nper) tables can be generated for each tJIT(per),act value.



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