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PM7345 Datasheet(PDF) 67 Page - PMC-Sierra, Inc |
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PM7345 Datasheet(HTML) 67 Page - PMC-Sierra, Inc |
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67 / 306 page ![]() PM7345 S/UNI-PDH DATA SHEET PMC-931011 ISSUE 6 SATURN USER-NETWORK INTERFACE PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 53 Status signals such as far end receive failure (FERF), the alarm indication signal, and the idle signal can be inserted when their transmission is enabled by internal register bits. FERF can also be automatically inserted on detection of any combination of LOS, OOF or RED, or AIS by the T3-FRMR. A valid pair of P-bits is automatically calculated and inserted by the T3-TRAN. When C-bit parity mode is selected, the path parity bits, and far end block error (FEBE) indications are automatically inserted. When enabled for C-bit parity operation, the FEAC channel is sourced by the XBOC bit-oriented code transmitter. The TNETOP bit in the S/UNI-PDH Data Link and FERF Control register controls the source of the path maintenance data link. If TNETOP is logic 0, the path maintenance data link messages are sourced by the XFDL data link transmitter. If TNETOP is a logic 1, the path maintenance data link messages are sourced from the TDLSIG input pin with an associated clock on TDLCLK. TDLSIG and TDLCLK are only available in the 100-pin PQFP package. When enabled for M23 operation, the C-bits are forced to logic 1 with the exception of the C-bit Parity ID bit (first C-bit of the first M-subframe), which is forced to toggle every M-frame. The T3-TRAN supports diagnostic modes in which it inserts parity or path parity errors, F-bit framing errors, M-bit framing errors, invalid X or P-bits, line code violations, or all-zeros. User control of each of the overhead bits in the DS3 frame is provided. Overhead bits may be inserted on a bit-by-bit basis from a user supplied data stream. An overhead clock (at 526 kHz) and a DS3 overhead alignment output are provided to allow for control of the user provided stream. 9.12 E3 Transmitter The E3 Transmitter (E3-TRAN) Block integrates circuitry required to insert the overhead bits into an E3 bit stream and produce an HDB3-encoded signal. The E3-TRAN is directly compatible with the G.751 and G.832 framing formats. The E3-TRAN generates the frame alignment signal and inserts it into the incoming serial stream based on either the G.751 or G.832 formats and an alignment pulse applied to it by the SPLT block. All overhead and status bits in each frame format can be individually controlled by register bits or by the transmit overhead stream. While in certain framing format modes, the E3-TRAN generates various overhead bytes according to the following: • in G.832 E3 format, the E3-TRAN: |
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