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PM7345 Datasheet(PDF) 96 Page - PMC-Sierra, Inc

Part # PM7345
Description  SATURN USER-NETWORK INTERFACE FOR ATM PLESIOCHRONOUS DIGITAL HIERARCHY DATACOM
PDF  306 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM7345 Datasheet(HTML) 96 Page - PMC-Sierra, Inc

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PM7345 S/UNI-PDH
DATA SHEET
PMC-931011
ISSUE 6
SATURN USER-NETWORK INTERFACE
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
82
PMON EXZS Count Registers. When EXZSO is set to logic 1, any excessive
zeros occurrences over an 85 bit period increments the PMON EXZS counter by
one. When EXZSO is set to logic 0, summed LCVs are accumulated in the
PMON EXZS Count Registers. A summed LCV is defined as the occurrence of
either BPVs not part of a valid B3ZS signature or 3 consecutive zeros (or
excessive zeros if EXZDET=1) occurring over an 85 bit period; each summed
LCV occurrence increment the PMON EXZS counter by one.
BPVO:
The BPVO bit enables only bipolar violations to indicate line code violations and
be accumulated in the PMON LCV Count Registers. When BPVO is set to logic
1, only BPVs not part of a valid B3ZS signature generate an LCV indication and
increment the PMON LCV counter. When BPVO is set to logic 0, both BPVs not
part of a valid B3ZS signature, and either 3 consecutive zeros or excessive zeros
generate an LCV indication and increment the PMON LCV counter.
AISONES:
The AISONES bit controls the pattern used to detect the alarm indication signal
(AIS) when both AISPAT and AISC bits in DS3 FRMR Configuration register
(08H) are logic 0; if either AISPAT or AISC are logic 1, the AISONES bit is
ignored. When a logic 0 is written to AISONES, the algorithm checks that a
framed all-ones payload pattern (1111...) signal is observed for a period of time
before declaring AIS. Only the payload bits are observed to follow an all-ones
pattern, the overhead bits (X, P, M, F, C) are ignored. When a logic 1 is written to
AISONES, the algorithm checks that an unframed all-ones pattern (1111...)
signal is observed for a period of time before declaring AIS. In this case all the
bits, including the overhead, are observed to follow an all-ones pattern. The valid
combinations of AISPAT, AISC, and AISONES bits are summarized below:



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