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DM504 Datasheet(PDF) 121 Page - Texas Instruments

Part # DM504
Description  SoC for Vision Analytics 12mm Package (ABE) Silicon Revision 2.0
PDF  211 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DM504 Datasheet(HTML) 121 Page - Texas Instruments

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121
DM504
www.ti.com
SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017
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Specifications
Copyright © 2016–2017, Texas Instruments Incorporated
Table 5-47. Timing Requirements for McASP2 (1) (continued)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
4
tw(ACLKRX)
Pulse duration, ACLKR/X high or low
Any Other Conditions
0.5R - 3
(3)
ns
IOSET1 only, ACLKX/AFSX (In Sync
Mode), ACLKR/AFSR (In Async
Mode), and AXR are all inputs
0.38R (3)
ns
5
tsu(AFSRX-ACLK)
Setup time, AFSR/X input valid before
ACLKR/X
ACLKR/X int
18.5
ns
IOSET1 (vout1_*): ACLKR/X ext in
IOSET1 (vout1_*): ACLKR/X ext out
4
ns
IOSET2 (gpmc_*): ACLKR/X ext in
IOSET2 (gpmc_*): ACLKR/X ext out
3
ns
6
th(ACLK-AFSRX)
Hold time, AFSR/X input valid after
ACLKR/X
ACLKR/X int
-1
ns
ACLKR/X ext in
ACLKR/X ext out
0.4
ns
7
tsu(AXR-ACLK)
Setup time, AXR input valid before
ACLKR/X
ACLKR/X int
18.5
ns
IOSET1 (vout1_*): ACLKR/X ext in
IOSET1 (vout1_*): ACLKR/X ext out
11.5
ns
IOSET2 (gpmc_*): ACLKR/X ext in
IOSET2 (gpmc_*): ACLKR/X ext out
3
ns
8
th(ACLK-AXR)
Hold time, AXR input valid after
ACLKR/X
ACLKR/X int
-1
ns
ACLKR/X ext in
ACLKR/X ext out
0.4
ns
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKR/X period in ns.
(3) R = ACLKR/X period in ns.
Table 5-48. Timing Requirements for McASP3 (1)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
1
tc(AHCLKRX)
Cycle time, AHCLKR/X
20
ns
2
tw(AHCLKRX)
Pulse duration, AHCLKR/X high or low
0.35P
ns
3
tc(ACLKRX)
Cycle time, ACLKR/X
20
ns
4
tw(ACLKRX)
Pulse duration, ACLKR/X high or low
0.5R - 3
ns
5
tsu(AFSRX-ACLK)
Setup time, AFSR/X input valid before
ACLKR/X
ACLKR/X int
18.2
ns
ACLKR/X ext in
ACLKR/X ext out
4
ns
6
th(ACLK-AFSRX)
Hold time, AFSR/X input valid after
ACLKR/X
ACLKR/X int
-1
ns
ACLKR/X ext in
ACLKR/X ext out
0.4
ns
tsu(AXR-ACLK)
Setup time, AXR input valid before
ACLKX
ACLKX int (ASYNC=0)
18.2
ns
ACLKR/X ext in
ACLKR/X ext out
11.5
ns
8
th(ACLK-AXR)
Hold time, AXR input valid after
ACLKX
ACLKX int (ASYNC=0)
-1
ns
ACLKR/X ext in
ACLKR/X ext out
-1
ns
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1 (NOT SUPPORTED)
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1



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