DM504 datasheet(122/211 Pages) TI1

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A30 A31

B30 B31 C0 C1

C2 C3

C31

AHCLKR/X (Falling Edge Polarity)

AHCLKR/X (Rising Edge Polarity)

AFSR/X (Bit Width, 0 Bit Delay)

AFSR/X (Bit Width, 1 Bit Delay)

AFSR/X (Bit Width, 2 Bit Delay)

AFSR/X (Slot Width, 0 Bit Delay)

AFSR/X (Slot Width, 1 Bit Delay)

AFSR/X (Slot Width, 2 Bit Delay)

AXR[n] (Data In/Receive)

ACLKR/X (CLKRP = CLKXP = 0)(A)

ACLKR/X (CLKRP = CLKXP = 1)(B)

SPRS91v_McASP_01

122

DM504

SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

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Specifications

(2) P = AHCLKR/X period in ns.

(3) R = ACLKR/X period in ns.

For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP

receiver is configured for falling edge (to shift data in).

For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP

receiver is configured for rising edge (to shift data in).

Figure 5-27. McASP Input Timing

Table 5-49, Table 5-50, Table 5-51 and Figure 5-28 present Switching Characteristics Over

Recommended Operating Conditions for McASP1 to McASP3.

Table 5-49. Switching Characteristics Over Recommended Operating Conditions for McASP1 (1)

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

tc(AHCLKRX)

Cycle time, AHCLKR/X

tw(AHCLKRX)

Pulse duration, AHCLKR/X high or low

0.5P -

2.5 (2)

tc(ACLKRX)

Cycle time, ACLKR/X

tw(ACLKRX)

Pulse duration, ACLKR/X high or low

0.5P -

2.5 (3)

DM504 Datasheet(PDF) 122 Page - Texas Instruments

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