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DM504 Datasheet(PDF) 119 Page - Texas Instruments |
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DM504 Datasheet(HTML) 119 Page - Texas Instruments |
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119 / 211 page ![]() cs sclk d[0] d[3:1] Bit n-1 Bit n-2 Bit 1 Bit 0 PHA=0 POL=0 Command Command Write Data Write Data Q4 Q7 Q2 Q3 Q1 Q6 Q6 Q5 SPRS85v_TIMING_OSPI1_04 Q8 Q9 Q6 119 DM504 www.ti.com SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017 Submit Documentation Feedback Specifications Copyright © 2016–2017, Texas Instruments Incorporated Figure 5-26. QSPI Write (Clock Mode 0) NOTE To configure the desired virtual mode the user must set MODESELECT bit and DELAYMODE bitfield for each corresponding pad control register. The pad control registers are presented in Table 4-26 and described in Device TRM, Chapter 14 - Control Module. CAUTION The IO timings provided in this section are only valid if signals within a single IOSET are used. The IOSETs are defined in Table 5-45. In Table 5-45 are presented the specific groupings of signals (IOSET) for use with QSPI. Table 5-45. QSPI IOSETs SIGNALS IOSET1 IOSET3 BALL MUX BALL MUX qspi1_sclk C1 1 C1 1 qspi1_rtclk D7 8 B4 5 qspi1_d0 C3 1 C3 1 qspi1_d1 C2 1 C2 1 qspi1_d2 B3 1 B3 1 qspi1_d3 A3 1 A3 1 qspi1_cs0 A4 1 A4 1 qspi1_cs1 C6 5 |
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