DM504 datasheet(116/211 Pages) TI1

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sclk

d[0]

d[3:1]

Bit n-1

Bit n-2

Bit 1

Bit 0

PHA=1

POL=1

Command

Read Data

Bit 1

Bit 0

Read Data

SPRS85v_TIMING_OSPI1_01

Q12

Q13

Q14

Q15

Q12

Q13

Q14

Q15

116

DM504

SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

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Specifications

Table 5-43. Switching Characteristics for QSPI (continued)

PARAMETER

DESCRIPTION

Mode

MIN

MAX

UNIT

td(SCLK-D1)

Delay time, sclk falling edge to d[1] transition

Default

Timing

Mode

-1

tena(CS-D1LZ)

Enable time, cs active edge to d[1] driven (lo-z)

-P-3.5

-P+2.5

tdis(CS-D1Z)

Disable time, cs active edge to d[1] tri-stated (hi-z)

-P-2.5

-P+2.0

td(SCLK-D1)

Delay time, sclk first falling edge to first d[1] transition

PHA=0

Only,

Default

Timing

Mode

-2

(1) The Y parameter is defined as follows: If DCLK_DIV is 0 or ODD then, Y equals 0.5. If DCLK_DIV is EVEN then, Y equals

(DCLK_DIV/2) / (DCLK_DIV+1). For best performance, it is recommended to use a DCLK_DIV of 0 or ODD to minimize the duty cycle

distortion. The HSDIVIDER on CLKOUTX2_H13 output of DPLL_PER can be used to achieve the desired clock divider ratio. All

required details about clock division factor DCLK_DIV can be found in the device TRM.

(2) P = SCLK period.

(3) M=QSPI_SPI_DC_REG.DDx + 1 when Clock Mode 0. M=QSPI_SPI_DC_REG.DDx when Clock Mode 3. N = 2 when Clock Mode 0. N

= 3 when Clock Mode 3.

Figure 5-23. QSPI Read (Clock Mode 3)

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