DM504 datasheet(115/211 Pages) TI1

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DM504

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SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

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Specifications

Table 5-42. McSPI1 IOSETs (continued)

SIGNALS

IOSET1

IOSET2

IOSET3

BALL

MUX

BALL

MUX

BALL

MUX

spi1_d1

spi1_d0

spi1_cs0

spi1_cs1

spi1_cs2

spi1_cs3

5.9.6.10 QSPI

The Quad SPI (QSPI) module is a type of SPI module that allows single, dual or quad read access to

external SPI devices. This module has a memory mapped register interface, which provides a direct

interface for accessing data from external SPI devices and thus simplifying software requirements. It

works as a master only. There is one QSPI module in the device and it is primary intended for fast

booting from quad-SPI flash memories.

General SPI features:

•

Programmable clock divider

•

Six pin interface (DCLK, CS_N, DOUT, DIN, QDIN1, QDIN2)

•

4 external chip select signals

•

Support for 3-, 4- or 6-pin SPI interface

•

Programmable CS_N to DOUT delay from 0 to 3 DCLKs

•

Programmable signal polarities

•

Programmable active clock edge

•

Software controllable interface allowing for any type of SPI transfer

NOTE

For more information, see the Quad Serial Peripheral Interface section of the Device TRM.

Table 5-43 and Table 5-44 present Timing and Switching Characteristics for Quad SPI Interface.

Table 5-43. Switching Characteristics for QSPI

PARAMETER

DESCRIPTION

Mode

MIN

MAX

UNIT

tc(SCLK)

Cycle time, sclk

Default

Timing

Mode,

Clock

Mode 0

10.4

Default

Timing

Mode,

Clock

Mode 3

15.625

tw(SCLKL)

Pulse duration, sclk low

Y*P-1 (1)

tw(SCLKH)

Pulse duration, sclk high

Y*P-1 (1)

td(CS-SCLK)

Delay time, sclk falling edge to cs active edge, CS3:0

Default

Timing

Mode

-M*P-1

(2) (3)

-M*P+1

(2) (3)

td(SCLK-CS)

Delay time, sclk falling edge to cs inactive edge, CS3:0

Default

Timing

Mode

N*P-1 (2)

(3)

N*P+1

(2) (3)

DM504 Datasheet(PDF) 115 Page - Texas Instruments

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