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DM504 Datasheet(PDF) 112 Page - Texas Instruments

Part # DM504
Description  SoC for Vision Analytics 12mm Package (ABE) Silicon Revision 2.0
PDF  211 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DM504 Datasheet(HTML) 112 Page - Texas Instruments

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spim_cs(OUT)
spi _sclk
m
(OUT)
spi _sclk
m
(OUT)
spi _
m d(IN)
spim_cs(OUT)
spi _sclk
m
(OUT)
spi _sclk
m
(OUT)
spi _
m d(IN)
Bit n-1
Bit n-2
Bit n-3
Bit n-4
Bit 0
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
PHA=0
EPOL=1
PHA=1
EPOL=1
POL=0
POL=1
POL=0
POL=1
SM8
SM9
SM3
SM1
SM2
SM1
SM8
SM9
SM3
SM1
SM2
SM1
SM2
SM3
SM2
SM3
SM4
SM5
SM4
SM5
SM4
SM4
SM5
SM5
SPRS91v_McSPI_02
112
DM504
SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017
www.ti.com
Submit Documentation Feedback
Specifications
Copyright © 2016–2017, Texas Instruments Incorporated
Figure 5-20. McSPI - Master Mode Receive
Table 5-41, Figure 5-21 and Figure 5-22 presents Timing Requirements for McSPI - Slave Mode.
Table 5-41. Timing Requirements for SPI - Slave Mode(5)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
SS1 (1)
(2)
tc(SPICLK)
Cycle time, spi_sclk
SPI1
25
ns
SPI2/3/4
33.3
ns
SS2 (1)
tw(SPICLKL)
(3)
Typical Pulse duration, spi_sclk low
0.45*P
ns
SS3 (1)
tw(SPICLKH)
(3)
Typical Pulse duration, spi_sclk high
0.45*P
ns
SS4 (1)
tsu(SIMO-SPICLK)
Setup time, spi_d[x] valid before spi_sclk active edge
2.82
ns
SS5 (1)
th(SPICLK-SIMO)
Hold time, spi_d[x] valid after spi_sclk active edge
2.82
ns
SS6 (1)
td(SPICLK-SOMI)
Delay time, spi_sclk active edge to mcspi_somi transition
SPI1
2
9.8
ns
SPI2/3/4
2
21
ns
SS7 (4)
td(CS-SOMI)
Delay time, spi_cs[x] active edge to mcspi_somi transition
16
ns



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