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DM504 Datasheet(PDF) 113 Page - Texas Instruments |
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DM504 Datasheet(HTML) 113 Page - Texas Instruments |
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113 / 211 page  spim _cs(IN) spi _sclk m (IN) spi _sclk m (IN) spi _ m d (OUT) spim _cs(IN) spi _sclk m (IN) spi _sclk m (IN) spi _ m d (OUT) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0 Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0 PHA=0 EPOL=1 POL=0 POL=1 POL=0 POL=1 PHA=1 EPOL=1 SS6 SS3 SS1 SS3 SS1 SS3 SS1 SS2 SS1 SS6 SS6 SS8 SS9 SS7 SS8 SS2 SS3 SS2 SS2 SS6 SS6 SS6 SS9 SPRS91v_McSPI_03 113 DM504 www.ti.com SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017 Submit Documentation Feedback Specifications Copyright © 2016–2017, Texas Instruments Incorporated Table 5-41. Timing Requirements for SPI - Slave Mode(5) (continued) NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT SS8 (1) tsu(CS-SPICLK) Setup time, spi_cs[x] valid before spi_sclk first edge 2.82 ns SS9 (1) th(SPICLK-CS) Hold time, spi_cs[x] valid after spi_sclk last edge 2.82 ns (1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture input data. (2) When operating the SPI interface in RX-only mode, the minimum Cycle time is 26ns (38.4MHz) (3) P = SPICLK period. (4) PHA = 0; SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register. (5) The IO timings provided in this section are applicable for all combinations of signals for spi1 and spi2. However, the timings are only valid for spi3 and spi4 if signals within a single IOSET are used. The IOSETs are defined in the following tables. Figure 5-21. McSPI - Slave Mode Transmit |
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